參數(shù)資料
型號： TMS0320F2810PBKAEP
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 94/159頁
文件大小： 2084K
代理商： TMS0320F2810PBKAEP
Electrical Specifications
94
March 2004 Revised October 2004
SGUS051A
Table 61. Typical Current Consumption by Various Peripherals (at 150 MHz)
PERIPHERAL MODULE
IDD CURRENT REDUCTION (mA)
12
eCAN
EVA
6
EVB
6
ADC
8
SCI
4
SPI
5
McBSP
13
All peripheral clocks are disabled upon reset. Writing to/reading from peripheral registers is possible only after the peripheral clocks
are turned on.
This number represents the current drawn by the digital portion of the ADC module. Turning off the clock to the ADC module results in the
elimination of the current drawn by the analog portion of the ADC (ICCA) as well.
6.8
Power Sequencing Requirements
320F2812/F2811/F2810/C2812/C2811/C2810 silicon requires dual voltages (1.8-V or 1.9-V and 3.3-V) to
power up the CPU, Flash, ROM, ADC, and the I/Os. To ensure the correct reset state for all modules during
power up, there are some requirements to be met while powering up/powering down the device. The current
F2812 silicon reference schematics (Spectrum Digital Incorporated eZdsp
board) suggests two options for
the power sequencing circuit.
Option 1:
In this approach, an external power sequencing circuit enables V
DDIO
first, then V
DD
and V
DD1
(1.8 V or
1.9 V). After 1.8 V (or 1.9 V) ramps, the 3.3 V for Flash (V
DD3VFL
) and ADC (V
DDA1
/V
DDA2
/AV
DDREFBG
)
modules are ramped up. While option 1 is still valid, TI has simplified the requirement. Option 2 is the
recommended approach.
Option 2:
Enable power to all 3.3-V supply pins (V
DDIO
, V
DD3VFL
, V
DDA1
/V
DDA2
/V
DDAIO
/AV
DDREFBG
) and then
ramp 1.8 V (or 1.9 V) (V
DD
/V
DD1
) supply pins.
1.8 V or 1.9 V (V
DD
/V
DD1
) should not reach 0.3 V until V
DDIO
has reached 2.5 V. This ensures the reset
signal from the I/O pin has propagated through the I/O buffer to provide power-on reset to all the modules
inside the device. See Figure 69 for power-on reset timing.
Power-Down Sequencing:
During power-down, the device reset should be asserted low (8
μ
s, minimum) before the V
DD
supply
reaches 1.5 V. This will help to keep on-chip flash logic in reset prior to the V
DDIO
/V
DD
power supplies
ramping down. It is recommended that the device reset control from “Low-Dropout (LDO)” regulators or
voltage supervisors be used to meet this constraint. LDO regulators that facilitate power-sequencing (with
the aid of additional external components) may be used to meet the power sequencing requirement. See
www.spectrumdigital.com for F2812 eZdsp
schematics and updates.
Table 62. Recommended “Low-Dropout Regulators”
SUPPLIER
PART NUMBER
Texas Instruments
TPS767D301
NOTE:
The GPIO pins are undefined until V
DD
= 1 V and V
DDIO
= 2.5 V.
eZdsp is a trademark of Spectrum Digital Incorporated.
相關(guān)PDF資料
PDF描述
TMS20F2810PBKAEP Digital Signal Processors
TMP20F2810PBKAEP Digital Signal Processors
TMS320F2812PGFMEP Digital Signal Processors
TMS320F2810PGFAEP Digital Signal Processors
TMX20F2810PBKAEP Digital Signal Processors
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMS06105 制造商:Traco Power 功能描述:TMS PCB mount SMPSU,5V 6W
TMS06112 制造商:Traco Power 功能描述:TMS PCB mount SMPSU,12V 6W
TMS06115 制造商:Traco Power 功能描述:TMS PCB mount SMPSU,15V 6W
TMS06124 制造商:Traco Power 功能描述:TMS PCB mount SMPSU,24V 6W
TMS06212 制造商:Traco Power 功能描述:TMS PCB mount SMPSU,+/-12V 6W
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*