參數(shù)資料
型號(hào): TMS0320F2810PBKAEP
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: Digital Signal Processors
中文描述: 數(shù)字信號(hào)處理器
文件頁數(shù): 117/159頁
文件大?。?/td> 2084K
代理商: TMS0320F2810PBKAEP
Electrical Specifications
116
March 2004 Revised October 2004
SGUS051A
Data Valid
11
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master In Data
Must Be Valid
Master Out Data Is Valid
1
7
6
10
3
2
SPISTE
In the master mode, SPISTE goes active 0.5tc(SPC) before valid SPI clock edge. On the trailing end of the word, the
SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 625. SPI Master External Timing (Clock Phase = 1)
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