參數(shù)資料
型號(hào): TMS0320F2810PBKAEP
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: Digital Signal Processors
中文描述: 數(shù)字信號(hào)處理器
文件頁數(shù): 91/159頁
文件大?。?/td> 2084K
代理商: TMS0320F2810PBKAEP
Electrical Specifications
91
March 2004 Revised October 2004
SGUS051A
6.4
Current Consumption by Power-Supply Pins Over Recommended Operating Conditions
During Low-Power Modes at 150-MHz SYSCLKOUT (320F281x)
MODE
TEST CONDITIONS
IDD
IDDIO
IDD3VFL
TYP
IDDA
TYP
MAX
TYP
MAX
MAX
TYP
MAX
Operational
All peripheral clocks are
enabled. All PWM pins are
toggled at 100 kHz.
Data is continuously
transmitted out of the
SCIA, SCIB, and CAN
ports. The hardware
multiplier is exercised.
Code is running out of
flash with 5 wait-states.
195 mA
230 mA
15 mA
30 mA
40 mA
45 mA
40 mA
50 mA
IDLE
Flash is powered down
XCLKOUT is turned off
All peripheral clocks
are on, except ADC
125 mA
150 mA
5 mA
10 mA
2
μ
A
4
μ
A
1
μ
A
20
μ
A
STANDBY
Flash is powered down
Peripheral clocks are
turned off
Pins without an internal
PU/PD are tied
high/low
5 mA
10 mA
5
μ
A
20
μ
A
2
μ
A
4
μ
A
1
μ
A
20
μ
A
HALT
Flash is powered down
Peripheral clocks are
turned off
Pins without an internal
PU/PD are tied
high/low
Input clock is disabled
70
μ
A
5
μ
A
20
μ
A
2
μ
A
4
μ
A
1
μ
A
20
μ
A
IDDA includes current into VDDA1, VDDA2, AVDDREFBG, and VDDAIO pins.
MAX numbers are at 125
°
C, and max voltage (VDD = 2.0 V; VDDIO, VDD3VFL, VDDA = 3.6 V).
NOTE:
HALT and STANDBY modes cannot be used when the PLL is disabled.
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