
Electrical Specifications
121
March 2004 Revised October 2004
SGUS051A
If the XREADY signal is sampled in the Synchronous mode (USEREADY = 1, READYMODE = 0), then:
1.
Lead:
LR
≥
t
c(XTIM)
LW
≥
t
c(XTIM)
AR
≥
2 x t
c(XTIM)
AW
≥
2 x t
c(XTIM)
2.
Active:
NOTE
: Restriction does not include external hardware wait states
These requirements result in the following XTIMING register configuration restrictions
:
XRDLEAD
≥
1
No hardware to detect illegal XTIMING configurations
XRDACTIVE
≥
1
XRDTRAIL
≥
0
XWRLEAD
≥
1
XWRACTIVE
≥
1
XWRTRAIL
≥
0
X2TIMING
0, 1
Examples of valid and invalid timing when using Synchronous XREADY
:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
Invalid
0
0
0
0
0
0
0, 1
Invalid
1
0
0
1
0
0
0, 1
Valid
No hardware to detect illegal XTIMING configurations
1
1
0
1
1
0
0, 1
If the XREADY signal is sampled in the Asynchronous mode (USEREADY = 1, READYMODE = 1), then:
1.
Lead:
LR
≥
t
c(XTIM)
LW
≥
t
c(XTIM)
AR
≥
2 x t
c(XTIM)
AW
≥
2 x t
c(XTIM)
2.
Active:
NOTE
: Restriction does not include external hardware wait states
3.
Lead + Active:
LR + AR
≥
4 x t
c(XTIM)
LW + AW
≥
4 x t
c(XTIM)
NOTE
: Restriction does not include external hardware wait states
These requirements result in the following XTIMING register configuration restrictions
:
XRDLEAD
≥
1
No hardware to detect illegal XTIMING configurations
or
XRDACTIVE
≥
2
XRDTRAIL
XWRLEAD
≥
1
XWRACTIVE
≥
2
XWRTRAIL
X2TIMING
0
0
0, 1
XRDLEAD
≥
2
No hardware to detect illegal XTIMING configurations
XRDACTIVE
≥
1
XRDTRAIL
XWRLEAD
≥
2
XWRACTIVE
≥
1
XWRTRAIL
X2TIMING
0
0
0, 1
Examples of valid and invalid timing when using Asynchronous XREADY
:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
Invalid
0
0
0
0
0
0
0, 1
Invalid
1
0
0
1
0
0
0, 1
Invalid
1
1
0
1
1
0
0
Valid
1
1
0
1
1
0
1
Valid
1
2
0
1
2
0
0, 1
Valid
No hardware to detect illegal XTIMING configurations
2
1
0
2
1
0
0, 1