參數(shù)資料
型號： TMS0320F2810PBKAEP
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 20/159頁
文件大?。?/td> 2084K
代理商： TMS0320F2810PBKAEP
Introduction
20
March 2004 Revised October 2004
SGUS051A
Table 22. Signal Descriptions
(Continued)
NAME
DESCRIPTION
PU/PD§
I/O/Z
PIN NO.
176-PIN
PGF
128-PIN
PBK
179-PIN
GHH
JTAG
TRST
B12
135
98
I
PD
JTAG test reset with internal pulldown. TRST, when driven
high, gives the scan system control of the operations of the
device. If this signal is not connected or driven low, the device
operates in its functional mode, and the test reset signals are
ignored.
NOTE: Do not use pullup resistors on TRST; it has an internal
pulldown device. In a low-noise environment, TRST can be
left floating. In a high-noise environment, an additional
pulldown resistor may be needed. The value of this resistor
should be based on drive strength of the debugger pods
applicable to the design. A 2.2-k
resistor generally offers
adequate protection. Since this is application-specific, it is
recommended that each target board is validated for proper
operation of the debugger and the application.
TCK
A12
136
99
I
PU
JTAG test clock with internal pullup
TMS
D13
126
92
I
PU
JTAG test-mode select (TMS) with internal pullup. This serial
control input is clocked into the TAP controller on the rising
edge of TCK.
TDI
C13
131
96
I
PU
JTAG test data input (TDI) with internal pullup. TDI is clocked
into the selected register (instruction or data) on a rising edge
of TCK.
TDO
D12
127
93
O/Z
JTAG scan out, test data output (TDO). The contents of the
selected register (instruction or data) is shifted out of TDO on
the falling edge of TCK.
EMU0
D11
137
100
I/O/Z
PU
Emulator pin 0. When TRST is driven high, this pin is used
as an interrupt to or from the emulator system and is
defined as input/output through the JTAG scan.
EMU1
C9
146
105
I/O/Z
PU
Emulator pin 1. When TRST is driven high, this pin is used
as an interrupt to or from the emulator system and is
defined as input/output through the JTAG scan.
ADC ANALOG INPUT SIGNALS
I
ADCINA7
B5
167
119
ADCINA6
D5
168
120
I
ADCINA5
E5
169
121
I
ADCINA4
A4
170
122
I
8-Channel analog inputs for Sample-and-Hold A. The ADC
pins should not be driven before VDDA1, VDDA2, and VDDAIO
pins have been fully powered up.
ADCINA3
B4
171
123
I
ADCINA2
C4
172
124
I
ADCINA1
D4
173
125
I
ADCINA0
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
I = Input, O = Output, Z = High impedance
§PU = pin has internal pullup; PD = pin has internal pulldown
A3
174
126
I
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