參數(shù)資料
型號: TMS0320F2810PBKAEP
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processors
中文描述: 數(shù)字信號處理器
文件頁數(shù): 54/159頁
文件大?。?/td> 2084K
代理商: TMS0320F2810PBKAEP
Peripherals
54
March 2004 Revised October 2004
SGUS051A
4
Peripherals
The integrated peripherals of the F281x and C281x are described in the following subsections:
32-Bit CPU-Timers 0/1/2
Three 32-bit CPU-Timers
Two event-manager modules (EVA, EVB)
Enhanced analog-to-digital converter (ADC) module
Enhanced controller area network (eCAN) module
Multichannel buffered serial port (McBSP) module
Serial communications interface modules (SCI-A, SCI-B)
Serial peripheral interface (SPI) module
Digital I/O and shared pin functions
4.1
There are three 32-bit CPU-timers on the F281x and C281x devices (CPU-TIMER0/1/2).
CPU-Timers 1 and 2 are reserved for the real-time OS (such as DSP/BIOS). CPU-Timer 0 can be used in user
applications. These timers are different from the general-purpose (GP) timers that are present in the Event
Manager modules (EVA, EVB).
NOTE:
If the application is not using DSP/BIOS, then CPU-Timers 1 and 2 can be used in the
application.
Borrow
Reset
Timer Reload
SYSCLKOUT
TCR.4
(Timer Start Status)
TINT
16-Bit Timer Divide-Down
TDDRH:TDDR
32-Bit Timer Period
PRDH:PRD
32-Bit Counter
TIMH:TIM
16-Bit Prescale Counter
PSCH:PSC
Borrow
Figure 41. CPU-Timers
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