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參數(shù)資料
| 型號(hào)： | TMS0320F2810PBKAEP |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Digital Signal Processors |
| 中文描述： | 數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 127/159頁(yè) |
| 文件大小： | 2084K |
| 代理商： | TMS0320F2810PBKAEP |
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Electrical Specifications
126
March 2004 Revised October 2004
SGUS051A
6.26
External Interface Ready-on-Read Timing With One External Wait State
Table 630. External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
PARAMETER
MIN
MAX
UNIT
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
td(XCOHL-XRDL)
td(XCOHL-XRDH
th(XA)XZCSH
th(XA)XRD
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
Delay time, XCLKOUT high to zone chip-select active low
1
ns
Delay time, XCLKOUT high/low to zone chip-select inactive high
2
3
ns
Delay time, XCLKOUT high to address valid
2
ns
Delay time, XCLKOUT high/low to XRD active low
1
ns
Delay time, XCLKOUT high/low to XRD inactive high
2
1
ns
Hold time, address valid after zone chip-select inactive high
ns
Hold time, address valid after XRD inactive high
ns
Table 631. External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)
MIN
MAX
UNIT
ta(A)
ta(XRD)
tsu(XD)XRD
th(XD)XRD
LR = Lead period, read access. AR = Active period, read access. See Table 625.
Access time, read data from address valid
(LR + AR) 14
AR 12
ns
Access time, read data valid from XRD active low
ns
Setup time, read data valid before XRD strobe inactive high
12
ns
Hold time, read data valid after XRD inactive high
0
ns
Table 632. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
§
MIN
MAX
UNIT
tsu(XRDYsynchL)XCOHL
th(XRDYsynchL)
te(XRDYsynchH)
tsu(XRDYsynchH)XCOHL
th(XRDYsynchH)XZCSH
§The first XREADY (Synch) sample occurs with respect to E in Figure 631:
E = (XRDLEAD + XRDACTIVE) tc(XTIM)
When first sampled, if XREADY (Synch) is found to be high, then the access will complete. If XREADY (Synch) is found to be low, it will be sampled
again each tc(XTIM) until it is found to be high.
For each sample (n) the setup time (D) with respect to the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE +n 1) tc(XTIM) tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Setup time, XREADY (Synch) low before XCLKOUT high/low
15
ns
Hold time, XREADY (Synch) low
12
ns
Earliest time XREADY (Synch) can go high before the sampling XCLKOUT edge
3
ns
Setup time, XREADY (Synch) high before XCLKOUT high/low
15
ns
Hold time, XREADY (Synch) held high after zone chip select high
0
ns
Table 633. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
MIN
MAX
UNIT
tsu(XRDYAsynchL)XCOHL
th(XRDYAsynchL)
te(XRDYAsynchH)
tsu(XRDYAsynchH)XCOHL
th(XRDYasynchH)XZCSH
The first XREADY (Asynch) sample occurs with respect to E in Figure 632:
E = (XRDLEAD + XRDACTIVE 2) tc(XTIM)
When first sampled, if XREADY (Asynch) is found to be high, then the access will complete. If XREADY (Asynch) is found to be low, it will be
sampled again each tc(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE 3 +n) tc(XTIM) tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Setup time, XREADY (Asynch) low before XCLKOUT high/low
11
ns
Hold time, XREADY (Asynch) low
8
ns
Earliest time XREADY (Asynch) can go high before the sampling XCLKOUT edge
3
ns
Setup time, XREADY (Asynch) high before XCLKOUT high/low
11
ns
Hold time, XREADY (Asynch) held high after zone chip select high
0
ns
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