參數(shù)資料
型號(hào)： TMC428
廠商： Electronic Theatre Controls, Inc.
英文描述： Intelligent Triple Stepper Motor Controller with Serial Peripheral Interfaces
中文描述： 三步進(jìn)電機(jī)智能控制器的串行外圍接口
文件頁(yè)數(shù)： 8/50頁(yè)
文件大小： 378K
代理商： TMC428
TMC428 DATA SHEET (V. 1.00 / February 12, 2001)
8
Copyright 2000, TRINAMIC Microchips GmbH
M I C R O C H I P S
8
Serial Peripheral Interfaces
The four pins named SCS_C, SCK_C, SDI_C, SDO_C form the serial micro controller interface of the
TMC428. The communication between the micro controller and the TMC428 takes place via 32 bit
datagrams of fixed length. Concerning communication, the μC is the master and the TMC428 is the slave,
with the TMC428 in turn being the master for the stepper motor driver daisy chain. Similar to the micro
controller interface, the TMC428 uses a four wire serial interface for communication with the stepper
motor driver daisy chain. The four pins named SCS_S, SCK_S, SDO_S, SDI_S form the serial stepper motor
driver interface. Stepper motor drivers with parallel inputs can be used in connection with the TMC428
with some additional glue logic.
Serial Peripheral Interface for μC
The serial micro controller interface of the TMC428 behaves as a simple 32 bit shift register shifting serial
data SDI_C in with the rising edge of the clock signal SCK_C and copying the content of the 32 shift
register with the rising edge of the selection signal nSCS_C into a buffer register of 32 bit length. The
serial interface of the TMC428 sends back data read from registers or read from internal RAM back
immediately via the signal SDO_C. It processes serial data synchronously to the clock signal CLK.
Because of the on-the-fly processing of the input data stream, the serial micro controller interface of the
TMC428 accepts the serial data clock signal SCK_C with at least a duration (tSCKCL + tSCKCH = 3*tCLK
+ 3 * tCLK) of a total number of six clock cycles of CLK as outlined in the timing diagram Figure 5. The
data signal from the micro controller changes with the falling level of the serial data clock input SCK_C.
The maximum duration (tSCKCL + tSCKCH) of the serial data clock signal SCK_C is unlimited. But three
clock cycles is the lower limit for the low level (tSCKCL
≥
3 * tCLK) of the serial data clock SCK_C and for
the high level (tSCKCH
≥
3 * tCLK) it.
A complete serial datagram frame has a fixed length of 32 bit. While the data transmission from the micro
controller to the TMC428 is idle, the low active serial chip select input nSCS_C and also the serial data
clock signal SCK_C are set to high. While the signal nSCS_C is high, the TMC428 assigns the status of the
internal low active interrupt signal named nINT to the serial data output SDO_C (Figure 5). The serial data
input SDI_C of the TMC428 has to be driven by the micro controller. In contrast to other SPI
devices, the SDO_C signal of the TMC428 is always driven. It will never be in high impedance ‘Z’.
TM
compatible
CLK
sdi_c_bit#31
sdo_c_bit#31
tPD
tSCKCL
tSCKCH
tSUCSC
tHDCSC
1 x SDI_C sampled
one full 32 bit datagram
nINT
SDO_C
SDI_C
SCK_C
nSCS_C
sdi_c_bit#30 . . . sdi_c_bit#1
sdo_c_bit#30 ... sdo_c_bit#1
30 x sampled SDI_C
sdi_c_bit#0
sdo_c_bit#0
nINT
1 x SDI_C sampled
tHDCSC
tSUCSC
tCLK
tDATAGRAMuC
Figure 5 - Timing diagram of the serial μC interface
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