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參數(shù)資料
| 型號： | TMC428 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Intelligent Triple Stepper Motor Controller with Serial Peripheral Interfaces |
| 中文描述： | 三步進(jìn)電機智能控制器的串行外圍接口 |
| 文件頁數(shù)： | 26/50頁 |
| 文件大小： | 378K |
| 代理商： | TMC428 |
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TMC428 DATA SHEET (V. 1.00 / February 12, 2001)
26
Copyright 2000, TRINAMIC Microchips GmbH
M I C R O C H I P S
26
parameter
lsmd
(
l
ast
s
tepper
m
otor
d
river). The two bit wide parameter
lsmd
has to be set to %00 for
one stepper motor driver, %01 for two stepper motor drivers, and %10 for three stepper motor drivers.
Five bits are proposed to change polarities to opposite polarity. The selection signal for the stepper motor
driver chain named
nSCS_S
is controlled by the polarity bit named
polarity_nscs_s.
The
nSCS_S
signal is
low active if this bit is set to ‘0’ it is high active if this bit is set to ‘1’. The polarity of the stepper motor
driver chain clock signal
SCK_S
is defined by the bit
polarity_sck_s
. If this bit is ‘0’ the clock polarity is
according to Figure 6 on page 3. The clock signal
SCK_S
is inverted If it is set to ‘1’. The bit
polarity_PH_AB
defines the polarity of the phase bits for the stepper motor. Inverting this bit changes
the rotation direction of the associated stepper motor. The bit
polarity_FD
defines the polarity of the fast
decay controlling bit.
If it is ‘0’ fast decay is high active and if it is ‘1’ fast decay is low active. The bit
named
polarity_DAC_AB
defines the polarity of the DAC bit vectors.
If it is ‘0’ the DAC bits are high
active and if it is ‘1’ the DAC bits are inverted – low active.
The bit named
csCommonIndividual
defines either a single chip select signal
nSCS_S
is used common
for all stepper motor driver chips (resp.
TMC288
/
TMC289
) or three chip select signals
nSCS_S
,
nCS2
,
nCS3
are use to select the stepper motor driver chips individually. This feature is available only for the
TMC428 within the larger SOIC24 package (
TMC428-PI24
) where the two additional chip select signals
nCS2
,
nCS3
are available (see Figure 2). The one common chip select signal
nSCS_S
is used if the bit
named
csCommonIndividual is
‘0’.
32 bit DATAGRAM send from a μC to the TMC428
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
R
ADDRESS
R
DATA
1 1 1 1 1 1
clk2_div
polarities
lsmd
0
m
r
c
c
p
p
p
p
p
l
Table 11 - Stepper Motor Global Parameter Register
The seven bits named
clk2_div
determine the clock frequency of the stepper motor driver chain clock
signal
SCK_S
. The frequency
f_sck_s[Hz]
of the stepper motor driver chain clock signal
SCK_S
is
f_sck_s[Hz] = f_clk[Hz] / ( 2 * (clk2_div+1) )
. A value of
127 (%1111111, $7F)
is the upper limit for
the parameter
clk2_div
. With
clk2_div = 127
the clock frequency of
SCK_S
is at minimum. Due to
internal processing, a value of
7 (%0000111, $07)
is the lower limit for the clock divider parameter
clk2_div
. With
clk2_div = 7
the clock frequency of
SCK_S
is at maximum. Due to internal processing, the
frequency of
SCK_S
does not become higher for
clk2_div < 7
, but the signal
SCK_S
becomes asymmetric
with respect to it’s duty cycle. An asymmetric duty cycle may cause male function of stepper motor
drivers, where stepper motor driver chips may work correctly in particular at low clock frequencies of
CLK
.
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