
TMC428 DATA SHEET (V. 1.00 / February 12, 2001)
30
Copyright 2000, TRINAMIC Microchips GmbH
M I C R O C H I P S
30
RAM Address Partitioning and Data Organization
The on-chip RAM capacity is 128 x 6 bit. These 128 on-chip RAM cells of 6 bit width are addressed via 64
addresses of 2 x 6 bit (see Table 12). So, from the point of view of addressing the on-chip RAM via
datagrams, the address space enfolds 64 addresses of 24 bit wide data, where only 2 x 6 = 12 bits are
relevant. These 64 addresses are partitioned– selected by the
RRS
(Register RAM Select, datagram bit 31)–
into two address ranges of 32 addresses. The registers of the TMC428 are addressed with RRS=’0’. The
on-chip RAM is addressed with RRS=’1’. The 64 on-chip RAM addresses are partitioned into two separated
ranges by the most significant address bit of the datagram (bit 30).
The first 32 addresses are proposed for the configuration of the serial stepper motor driver chain. Each of
these 32 addresses stores two configuration words, composed of the so called NxM (
N
e
x
t
M
otor) bit
together with the 5 bit wide primary signal code. While sending a datagram, the primary signal code
words are read internally beginning with the first address of the driver chain datagram configuration
memory range. Each primary signal code word selects a signal proposed by the micro step unit. If the NxM
bit is ‘1’ an internal stepper motor addressing counter is incremented. If this internal counter is equivalent
to the lsmd (last stepper motor driver) parameter, the datagram transmission is finished and the counter is
preset to %00 for the next datagram transmission to the stepper motor driver chain.
The second 32 addresses are proposed to store the micro step table, which might be a quarter sine wave
period as a basic approach or the quarter period of an periodic function optimized for micro stepping of a
given stepper motor type. Different stepper motors may step with different micro step resolutions, but the
micro step look up table (LUT) is the same for all stepper motors controlled by one TMC428. Any quarter
wave period stored in the micro step table is expanded automatically to a full period wave together with
its 90° phase shifted wave.
32 bit DATAGRAM send from a μC to the TMC428 via pin SDI_C
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
DATA
R
ADDRESS
R
data @ odd RAM
addresses
data @ even
RAM addresses
1
0
32 x (2x6 bit)
driver chain
datagram
configuration
range
N
signal_codes
N
signal_codes
1
1
32 x (2x6 bit)
quarter
period sine
wave LUT
range
quarter sine wave
values (amplitude)
quarter sine wave
values (amplitude)
Table 12 - Partitioning of the On-Chip RAM address space