參數(shù)資料
型號(hào)： TMC428
廠(chǎng)商： Electronic Theatre Controls, Inc.
英文描述： Intelligent Triple Stepper Motor Controller with Serial Peripheral Interfaces
中文描述： 三步進(jìn)電機(jī)智能控制器的串行外圍接口
文件頁(yè)數(shù)： 12/50頁(yè)
文件大?。?/td> 378K
代理商： TMC428
TMC428 DATA SHEET (V. 1.00 / February 12, 2001)
12
Copyright 2000, TRINAMIC Microchips GmbH
M I C R O C H I P S
12
the micro controller has to disable its interrupt input while it sends a datagram to the TMC428, because
SDO_C signal– driven by the TMC428 –alternates during datagram transmission.
For initialization purposes, the TMC428 enables direct communication between the micro controller and
the stepper motor driver chain by sending a so called
cover datagram
. The position
cover_position
and
actual length
cover_len
of a cover datagram is specified by writing them into a common register. Writing
an up to 24 bit wide cover datagram to the register
cover_datagram
will fade in that cover datagram
into the next datagram send to the stepper motor driver chain. As a default setting, the TMC428 only
sends datagrams on demand. Optionally, continuous update – periodic sending of datagrams to the
stepper motor driver chain – is also possible. So, the status bit named
CDGW
(cover datagram waiting) is a
handshake signal for the micro controller in regard to the datagram covering mechanism. This feature is
necessary to enable direct data transmission from a micro controller to the stepper motor driver chips for
initialization purposes.
The status bits
RS3, RS2, RS1
represent the settings of the reference switches. But, the reference switch
inputs REF3, REF2, REF1 are not mapped directly to these status bits. Rather, the reference switch inputs
may have different functions, depending on programming (see page 20). The three status bits
xEQt3,
xEQt2, xEQt1
indicate individually for each stepper motor, if it has reached its target position. The status
bits
RS3, RS2, RS1
and bits
xEQt3, xEQt2, xEQt1
can trigger an interrupt or enable simple polling
techniques.
Simple Datagram Examples
The % prefix– normally indicating binary representation in this data sheet –is omitted for the following
datagram examples. Assuming, one would like to write (rw=
0
) to a register (rrs=
0
) at the address
%001101 the following data word %0000 0000 0000 0001 0010 0011, one would have to send the
following 32 bit datagram
0
110011
0
000000000000000100100011
to the TMC428. With inactive interrupt (nINT=1), no cover datagram waiting (CDGW=0), all reference
switches inactive (RS3=0, RS2=0, RS1=0), and all stepper motors at target position (xEQt3=1, xEQt2=1,
xEQt1=1) the status bits would be %
10010101
the TMC428 would send back the 32 bit datagram:
10010101
000000000000000000000000
To read (rw=
1
) back that register write before, one would have to send the 32 bit datagram
0
110011
1
000000000000000000000000
to the TMC428 and would get back from it the datagram
10010101
000000000000000100100011.
Write (rw=
0
) access to on-chip RAM (rrs=
1
) to an address %111111 occurs similar to register access, but
with rrs=1. To write two 6 bit data words %100001 and %100011 to successive pair-wise RAM addresses
%1111110 and %1111111 (%100001 to %1111110 and %100011 to %1111111) which are commonly
addressed by one datagram (see pages 13 and 29), one would have to send the datagram
1
111111
0
000000000010001100100001.
To read (rw=
1
) from that on-chip memory address, one would have to send the datagram
1
111111
1
000000000000000000000000.
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