參數(shù)資料
型號(hào)： TMC428
廠商： Electronic Theatre Controls, Inc.
英文描述： Intelligent Triple Stepper Motor Controller with Serial Peripheral Interfaces
中文描述： 三步進(jìn)電機(jī)智能控制器的串行外圍接口
文件頁(yè)數(shù)： 11/50頁(yè)
文件大小： 378K
代理商： TMC428
TMC428 DATA SHEET (V. 1.00 / February 12, 2001)
11
Copyright 2000, TRINAMIC Microchips GmbH
M I C R O C H I P S
11
Datagram Structure
The micro controller (μC) communicates with the TMC428 via the four wire (nSCS_C, SCK_C, SDI_C,
SDO_C) serial interface. Each datagram send to the TMC428 via the pin SDI_C and each datagram
received from the TMC428 via the pin SDO_C is 32 bit long. The first bit send is the MSB (most significant
bit named sdi_c_bit#31 at Figure 5). The last bit send is the LSB (least significant bit named sdi_c_bit#0 at
Figure 5). During reception of a datagram, the TMC428 immediately sends back a datagram of the same
length to the micro controller. That datagram send back is the result of the request given by the datagram
from the micro controller.
A request to read out one register of the TMC428 immediately turns back a datagram with the contents
of that register addressed by the datagram send from the micro controller. In case of writing data into
registers, the TMC428 sends back 8 status bits and 24 data bits set to ‘0’. Datagrams send from the micro
controller to the TMC428 have the form:
32 bit DATAGRAM send from a μC to the TMC428 via pin SDI_C
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
R
ADDRESS
R
DATA
The 32 bit wide datagrams send to the TMC428 are assorted in four groups of bits:
RRS
(register RAM
select) selecting either registers or on-chip RAM;
ADDRESS
bits addressing memory within the register set
or within the RAM area;
RW
(read write) bit distinguishing between read access and write access;
DATA
bits for write access– for read access these bits are
don’t care
and should be set to ‘0‘. Different internal
registers of the TMC428 have different lengths. So, for some registers only a subset of these 24 data bit is
really necessary, and unnecessary data bits should be set to ‘0‘. Some addresses access more than a single
register simultaneously. In that cases, unnecessary data bits should also be set to ‘0‘.
The 32 bit wide datagrams received by the μC from the TMC428 are assorted in two groups of bits:
STATUS BITS
and
DATA BITS
. The status bits, send back with each datagram, carry the most important
information about internal states of the TMC428 and the settings of the reference switches. These
datagrams have the form:
32 bit DATAGRAM send back from the TMC428 to a μC via pin SDO_C
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
DATA BITS
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
STATUS BITS
SM3 SM2 SM1
n
C
R
x
R
x
R
x
The status bit
nINT
is the internal low active interrupt controller output signal. Handling of interrupt
conditions without using interrupt techniques is possible by polling this status bit. The interrupt signal is
also directly available at the SDO_C pin of the TMC428 if nSCS_C is high. The pin SDO_C may directly be
connected to an interrupt input of the micro controller. Because the SDO_C / nINT output is multiplexed,
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