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參數(shù)資料
| 型號： | TMC428 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Intelligent Triple Stepper Motor Controller with Serial Peripheral Interfaces |
| 中文描述： | 三步進電機智能控制器的串行外圍接口 |
| 文件頁數(shù)： | 10/50頁 |
| 文件大?。?/td> | 378K |
| 代理商： | TMC428 |
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TMC428 DATA SHEET (V. 1.00 / February 12, 2001)
10
Copyright 2000, TRINAMIC Microchips GmbH
M I C R O C H I P S
10
The bit mapping for each stepper motor driver is composed of so called
primary signal bits
provided by the
micro step unit of the TMC428 individually for each stepper motor. Each primary signal bit is represented
by a five bit code word called
primary signal code
. The order of primary signal bits to be send to the
stepper motor driver daisy chain is defined by the order of primary signal code words in the configuration
RAM area. To distinguish different stepper motor drivers, an additional bit called
next motor bit
(NxM-Bit)
is prefixed to the five bit wide primary signal code words. So, the total data word width is six bit. Each
NxM-Bit effects an incrementation of an internal stepper motor address until processing– sending serially
datagram bits –of the last stepper motor is completed. For this, a parameter called LSMD (last stepper
motor driver) has to be programmed during initialization after power up. So, the codes written into the
serial interface configuration RAM area represent the mapping of control signals provided by the micro
step units to control bits of the drivers. It might be noted here, that configuring the serial driver interface
is much easier as it might seem here. It is explained in detail, illustrated by examples below.
The timing of the serial driver interface is programmable in a wide range. The clock divider provides 16 up
to 512 clock cycles (tCLK) for a serial driver interface data clock period. The default duration of a clock
period (tSCKCL+tSCKCH) of the signal nSCS_S is 16+16=32 clock periods of the clock signal CLK. The
minimal duration of a serial interface clock period (tSCKCL+tSCKCH) is 8+8=16 clock cycles of signal CLK
as outlined in
Figure 6. Also, the polarities of the signals nSCS_S and SCK_S are programmable to use
driver chips from other vendors with inverted polarities without additional glue logic.
The input SDI_S of the serial driver interface must always be driven to a defined level. So, to avoid high
impedance (‘Z’) at that input pin, a pull-up resistor or a pull-down resistor of 10 K
is necessary at that
input, if the stepper motor driver chain is idle.
Symbol
tSUCSC
tHDCSC
tSCKCL
tSCKCH
tDAMAGRAMuC
tDAMAGRAMuC
fCLK
tCLK
tPD
Parameter
Setup Clocks for nSCS_C
Hold Clocks for nSCS_C
Serial Clock Low
Serial Clock High
Datagram Length
Datagram Length
Clock Frequency
Clock Period tCLK = 1 / fCLK
CLK-rising-edge-to-Output Propagation Delay
Min
Typ
Max
∞
∞
∞
∞
∞
∞
16
∞
Unit
3
3
3
3
3+3 + 32*6 + 3+3 = 204
12.75
0
62.5
CLK periods
CLK periods
CLK periods
CLK periods
CLK periods
μs
MHz
ns
ns
5
Table 2 - Timing Characteristics of the Serial Microcontroller Interface
Symbol
tSUSCS
tHDSCS
tCKSL
tCKSH
tDAMAGRAMdrv
tDAMAGRAMdrv
fCLK
tCLK
tPD
Parameter
Min
8
8
8
8
Typ
16
16
16
16
Max
256
256
256
256
Unit
CLK periods
CLK periods
CLK periods
CLK periods
CLK periods
μs
MHz
ns
ns
Datagram Length
Datagram Length
Clock Frequency
Clock Period tCLK = 1 / fCLK
CLK-rising-edge to Outputs Delay
8+8+1*16+8+8=48
3
0
62.5
512+64*512+512= 33792
2112
16
∞
5
Table 3 - Timing Characteristics of the Serial Stepper Motor Driver Interface
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