參數(shù)資料
型號(hào)： TI380PCM
廠商： Texas Instruments, Inc.
英文描述： PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
中文描述： PCI總線接口，可用于TI380 COMMPROCESSORS
文件頁(yè)數(shù)： 9/40頁(yè)
文件大?。?/td> 530K
代理商： TI380PCM
TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS035 – JUNE 1997
9
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Terminal Functions (Continued)
TERMINAL
NAME
DESCRIPTION
I/O
NO.
PCI INTERFACE
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD09
AD08
AD07
AD06
AD05
AD04
AD03
AD02
AD01
AD00
27
29
30
32
33
35
36
38
42
43
44
45
47
48
49
51
66
68
69
71
72
73
74
75
78
80
81
83
84
85
86
87
I/O
PCI address and data. A bus transaction to or from one of these pins consists of an address phase
followed by one or more data phases.
The address phase is the clock cycle in which FRAME is asserted. During the address phase,
AD31–AD00 contain a physical address (32 bits). For I/O, this is a byte address; for configuration and
memory, it is a DWORD address. During data phases, AD07–AD00 contain the LSB, and AD31–AD24
contain the MSB. Write data is stable and valid when IRDY is asserted, and read data is stable and valid
when TRDY is asserted. Data is transferred during those clocks where both IRDY and TRDY are
asserted.
C/BE3
C/BE2
C/BE1
C/BE0
39
53
65
77
I/O
Bus command and byte-enables. During the address phase of a transaction, C/BE3–C/BE0 define the
bus command. During the data phase, C/BE3–C/BE0 are used as byte-enables. The byte-enables are
valid for the entire data phase and they determine which byte lanes carry meaningful data. C/BE0
applies to the LSB and C/BE3 applies to the MSB.
DEVSEL
59
I/O
Device-select. When DEVSEL is actively driven, it indicates that the driving device has decoded its
address as the target of the current access. As an input, DEVSEL indicates if any device on the bus
has been selected. If no PCI agent has asserted DEVSEL, then the TI380PCIA removes itself as the
PCI bus master.
I = in, O = out
The TI380PCIA SIF pin names correspond to a subset of the system interface pins on a TI380C2x§. See the TI380C2x§ data sheets for more
information on individual pins. Like-named pins on the TI380PCIA and TI380C2x§ system interfaces are intended to be connected to each
other.
§TI380C3x devices can be used with TI380PCIA in the same way as TI380C2x devices.
Typical bit-ordering for Intel
and Motorola
processor buses
#The signal connecting this pin to the TI380C2x§ also should be connected to a 4.7-k
pullup resistor.
||The TI380PCIA BIF pin names correspond to a subset of the local memory bus interface pins on a TI380C2x§. Like-named pins on the two
devices are intended to be connected to each other. Consult the TI380C2x§ data sheets for more information on individual pins.
NOTE 1: The TI380PCIA allows driver software to set SBCLK output to a steady high state. This signal is driven to a steady high state during
power-down operations.
A
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