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參數(shù)資料
| 型號： | TI380PCM |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS |
| 中文描述： | PCI總線接口，可用于TI380 COMMPROCESSORS |
| 文件頁數(shù)： | 21/40頁 |
| 文件大?。?/td> | 530K |
| 代理商： | TI380PCM |
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TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS035 – JUNE 1997
21
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
device identification
The TI380PCIA contains the device identification information in its configuration space as shown in Table 5.
Table 5. Device Identification
REGISTER
HEX VALUE
Vendor ID
104Ch
0508h
Device ID
Revision ID
01
Class code
028000
Header type
These values are defaults and can be overwritten by the
contents of the optional EEPROM.
00
command register—configuration space DWORD address (0x04)
Figure 8 shows the command register layout.
Fast Back-to-Back Enable
SERR Enable
Wait-Cycle Control
Parity-Error Response
VGA Palette Snoop
Memory Write-and-Invalidate Enable
Special Cycles
Bus Master
Memory Space
I/O Space
Reserved
15
10
9
8
7
6
5
4
3
2
1
0
0
0
0
Figure 8. Command Register Layout
The command register provides coarse control over the TI380PCIA’s ability to generate and to respond to PCI
cycles. When 0 is written to this register, the device is logically disconnected from the PCI bus for all accesses
except configuration accesses.
The command register is set to 0 at power up and after hardware reset.
Bit 00:
I/O space. Controls the TI380PCIA’s response to I/O space accesses. A value of 0 disables the
TI380PCIA’s response. A value of 1 allows the TI380PCIA to respond to I/O space accesses.
Bit 01:
Memory space. Controls the TI380PCIA’s response to memory space accesses. A value of 0 disables
the TI380PCIA’s response. A value of 1 allows the TI380PCIA to respond to memory space accesses.
Bit 02:
Bus master. Controls the TI380PCIA’s ability to act as a master on the PCI bus. A value of 0 disables
TI380PCIA from generating PCI accesses. A value of 1 allows the TI380PCIA to behave as a bus master. If the
automatic software-reset bit in the TI380PCIA interface control register (0x54) is set to a one, then the action
of clearing the bus master bit of the TI380PCIA command register from one to zero also resets the TI380PCIA.
A
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