參數(shù)資料
型號： TI380PCM
廠商： Texas Instruments, Inc.
英文描述： PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
中文描述： PCI總線接口，可用于TI380 COMMPROCESSORS
文件頁數(shù)： 22/40頁
文件大?。?/td> 530K
代理商： TI380PCM
TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS035 – JUNE 1997
22
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
command register—configuration space DWORD address (0x04) (continued)
Bit 03:
Special cycles. Allows the LAN subsystem to enter low-power mode following a shutdown broadcast.
All other special-cycle messages are ignored. Device drivers must reinitialize and download microcode to the
LAN subsystem when the subsystem exits low-power mode.
Bit 04:
Memory write-and-invalidate enable. Controls memory write-and-invalidate cycles. A value of 1 enables
the TI380PCIA to generate memory write-and-invalidate cycles. When this bit is 0, the memory-write command
must be used instead.
Bit 05:
VGA palette snoop. Applies to video graphics adapter (VGA) subsystems and is hardwired to 0
Bit 06:
Parity error response. This bit controls the TI380PCIA response to parity errors. When this bit is set
to 1, the TI380PCIA takes its normal action when a parity error is detected. When this bit is reset to 0, the
TI380PCIA ignores any parity errors that it detects and continues normal operation. This bit is set to 0 after reset.
Bit 07:
Wait-cycle control. This bit is hardwired to 0 because the TI380PCIA does not support
address/data-stepping.
Bit 08:
SERR enable. This bit is an enable bit for the SERR driver. A value of 0 disables the SERR driver and
a value of 1 enables it. The state of this bit after RST is 0.
Bit 09:
Fast back-to-back enable. This bit is hardwired to 0 because the TI380PCIA does not support fast
back-to-back transactions to different devices.
Bits 10–15:
Reserved. These reserved bits are read as 0.
status register—configuration space DWORD address (0x04)
Figure 9 shows the status register layout.
Fast Back-to-Back Capability
Data Parity Detection
DEVSEL Timing
00 – Fast
01 – Medium
10 – Slow
Signal Target Abort
Receive Target Abort
Receive Master Abort
Signal System Error
Detect Parity Error
Reserved
14
12
0
15
10
9
8
7
6
0
1
0
13
11
Figure 9. Status Register Layout
The status register records status information for PCI bus-related events. Reads from this register behave
normally. Writes are slightly different in that bits can be reset to 0, but not set to 1. A bit is reset whenever data
is written to the register and the corresponding bit of the written data contains a 1.
A
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