參數(shù)資料
型號： TI380PCM
廠商： Texas Instruments, Inc.
英文描述： PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
中文描述： PCI總線接口，可用于TI380 COMMPROCESSORS
文件頁數(shù)： 23/40頁
文件大?。?/td> 530K
代理商： TI380PCM
TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS035 – JUNE 1997
23
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
status register—configuration space DWORD address (0x04) (continued)
Bits 00–06:
Reserved
Bit 07:
Fast back-to-back capability. This bit is hardwired to 0 because the TI380PCIA does not support fast
back-to-back cycles as a slave.
Bit 08:
Data-parity detection. This bit is set to 1 when three conditions are met: 1) the PCI device asserted PERR
itself or observed PERR asserted; 2) the device setting the bit acted as the bus master for the operation in which
the error occurred; 3) the parity error response bit (in the command register) is set.
Bits 09–10:
DEVSEL timing. DEVSEL timing for the TI380PCIA is set to 01 (medium).
Bit 11:
Signal target abort. This bit is set to 1 whenever TI380PCIA terminates a transaction with slave abort.
Bit 12:
Receive target abort. This bit is set to 1 whenever a transaction from the TI380PCIA is terminated with
slave abort.
Bit 13:
Receive master abort. This bit is set to 1 whenever a transaction from the TI380PCIA is terminated with
master abort.
Bit 14:
Signal system error. This bit is set whenever TI380PCIA asserts SERR.
Bit 15:
Detect parity error. This bit is set by TI380PCIA whenever it detects a parity error, even if parity-error
handling is disabled (as controlled by the parity error response bit in the command register).
miscellaneous functions
cache line size (CLS)—configuration space DWORD address (0x0C)
The CLS register is loaded with the host system data cache line size. On reset, it is set to 0. The value in this
register controls the TI380PCIA FIFO fill/flush algorithm. The value in this register should be a power of two
that is greater than or equal to 4, or a sum of those powers of two.
latency timer (LT)—configuration space DWORD address (0x0C)
The TI380PCIA supports burst data transfer on the PCI bus; therefore, a latency timer register is needed as
defined in the PCI specification.
header type — configuration space DWORD address (0x0C)
This register defines the layout of DWORD addresses 0x10–0x3C in the configuration space header. The
TI380PCIA supports only header type 0x00; therefore, contents of the header type register are read as 0.
built-in self-test (BIST)—configuration space DWORD address (0x0C)
The TI380PCIA does not support built-in self-test and returns 0 when the BIST register is read.
A
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