參數(shù)資料
型號(hào)： TI380PCM
廠商： Texas Instruments, Inc.
英文描述： PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
中文描述： PCI總線接口，可用于TI380 COMMPROCESSORS
文件頁數(shù)： 28/40頁
文件大?。?/td> 530K
代理商： TI380PCM
TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS035 – JUNE 1997
28
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
board configuration register (board config)—configuration space DWORD address (0x44)
Figure 14 shows the board configuration register layout.
0
0
0
0
7
31
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 14. Board Configuration Register Layout
Bits 00–07:
When RST is driven high, the value on ROMA[07:00] is latched into the board configuration register
in the TI380PCIA configuration space. The value on ROMA[07:00] can be provided by pullup and pulldown
resistors that do not affect operation after reset. This feature allows designers to support jumpers or
board-stuffing options that can be sensed by software that reads the board configuration register. If pullup and
pulldown resistors are not used, the contents of the board configuration register are undefined after reset.
Bits 08–31:
These bits must read as 0.
EEPROM read/write register — configuration space DWORD address (0x48)
Figure 15 shows the layout of the EEPROM read/write register. Table 8 describes bits 4 through 8 of this
register.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rsvd
rsvd
rsvd
rsvd
rsvd
rsvd
rsvd
ECR-
CERR
NEP
ECLK
EEN
EDATA
rsvd
rsvd
rsvd
rsvd
rsvd = reserved
Figure 15. EEPROM Read/Write Register Layout
Table 8. EEPROM Read/Write Register Bit Descriptions
BIT
DESCRIPTION
NO.
NAME
8
ECRCERR
EEPROM CRC error detected. ECRCERR is normally 0 but is set to 1 if an error is detected in the CRC read from
the EEPROM at power up. If this bit is set, the TI380PCIA also sets bit 7, the NEP bit.
7
NEP
EEPROM not present. NEP indicates that the EEPROM interface was disabled either by a pulldown resistor on the
EDIO pin or by the detection of an error in the checksum during the EEPROM download process.
6
ECLK
EEPROM serial I/O (SIO) clock. ECLK controls the state of the EDC pin.
1 = pin high
0 = pin low
5
EEN
EEPROM enable. EEN controls the direction of the EDIO pin. When this bit is set to a 1, the EDIO pin is driven with
a value in the EDATA bit.
4
EDATA
EEPROM data. EDATA is used to read or write the EDIO data pin on the EEPROM. When bit 5 is a 1, the EEPROM
data pin (EDIO) is driven with the value of this bit. If bit 5 is a 0, this bit becomes a 1 because EDIO is an open-drain
output.
A
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