參數(shù)資料
型號(hào)： TI380PCM
廠商： Texas Instruments, Inc.
英文描述： PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
中文描述： PCI總線接口，可用于TI380 COMMPROCESSORS
文件頁(yè)數(shù)： 6/40頁(yè)
文件大小： 530K
代理商： TI380PCM
TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS035 – JUNE 1997
6
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Terminal Functions (Continued)
TERMINAL
NAME
DESCRIPTION
I/O
NO.
SYSTEM INTERFACE (SIF) (CONTINUED)
Bus error. SBERR corresponds to the bus error signal of the 68000 microprocessor. SBERR is driven
low during a DMA cycle to indicate to the TI380C2x§ that the cycle must be terminated. See
Section 3.4.5.3 of the TMS380 Second-Generation Token Ring User’s Guide(SPWU005) for more
information.
SBERR
7
O
SBGR
5
O
System-bus grant. SBGR serves as an active-low bus grant, as defined in the standard 68000 interface.
H =
L
SIF bus release. SBRLS indicates to the TI380C2x§ that a higher-priority device requires the SIF bus.
The value on SBRLS is ignored by the TI380C2x§ when DMA is not performed.
System bus not granted
System bus granted
=
SBRLS
11
O
H =
L
The TI380C2x§ can hold onto the system bus.
The TI380C2x§ should release the system bus upon completion of current DMA cycle. If the
DMA transfer is not yet complete, the SIF rearbitrates for the SIF bus.
=
SBRQ
129
I
System-bus request. SBRQ is used to request control of the system bus in preparation for a DMA
transfer. SBRQ is internally synchronized to SBCLK.
H =
L
System chip select. SCS activates the system interface of the TI380C2x§ for a DIO read or write.
System bus not requested
System bus requested
=
SCS
12
O
H =
L
Not selected
Selected
=
SDBEN
127
I
System data-bus enable. SDBEN causes the TI380PCIA to allow its external data buffers to begin
driving data. SDBEN is accepted during both DIO and DMA.
H =
L
Keep external data buffers in high impedance state
Cause external data buffers to begin driving data
=
SDTACK
125
I/O
System data-transfer acknowledge. The purpose of SDTACK is to indicate to the bus master that a data
transfer is complete. SDTACK is internally synchronized to SBCLK by the TI380C2x§. During DMA
cycles, it is asserted before the falling edge of SBCLK in state T2 by the TI380PCIA to prevent a wait
state. SDTACK is an input when the TI380C2x§ is selected for DIO, and an output otherwise.#
H =
L
System bus NOT ready
Data transfer is complete; system bus is ready.
=
SHALT
3
O
System halt/bus error retry. If SHALT is asserted along with bus error (SBERR), the adapter retries the
last DMA cycle. This is the rerun operation as defined in the 68000 specification. See Section 3.4.5.3
of the TMS380 Second-Generation Token Ring User’s Guide(SPWU005) for more information.
System interrupt request. TI380C2x§ drives SIRQ to signal an interrupt request to the host processor.
SIRQ
6
I
H =
L
No interrupt request
Interrupt request by TI380C2x§
=
I = in, O = out
The TI380PCIA SIF pin names correspond to a subset of the system interface pins on a TI380C2x§. See the TI380C2x§ data sheets for more
information on individual pins. Like-named pins on the TI380PCIA and TI380C2x§ system interfaces are intended to be connected to each
other.
§TI380C3x devices can be used with TI380PCIA in the same way as TI380C2x devices.
Typical bit-ordering for Intel
and Motorola
processor buses
#The signal connecting this pin to the TI380C2x§ also should be connected to a 4.7-k
pullup resistor.
||The TI380PCIA BIF pin names correspond to a subset of the local memory bus interface pins on a TI380C2x§. Like-named pins on the two
devices are intended to be connected to each other. Consult the TI380C2x§ data sheets for more information on individual pins.
NOTE 1: The TI380PCIA allows driver software to set SBCLK output to a steady high state. This signal is driven to a steady high state during
power-down operations.
A
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