參數(shù)資料
型號(hào)： TI380PCM
廠商： Texas Instruments, Inc.
英文描述： PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
中文描述： PCI總線接口，可用于TI380 COMMPROCESSORS
文件頁(yè)數(shù)： 35/40頁(yè)
文件大?。?/td> 530K
代理商： TI380PCM
TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS035 – JUNE 1997
35
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
measure and test condition parameters (see Figure 20 and Figure 21)
SYMBOL
5-V SIGNALING
UNITS
Vth
Vtl
Vtest
Vmax
2.4
V
0.4
V
1.5
V
2.0
V
Input signal edge rate
1
V/ns
timing requirements (5-V signaling environment) (see Figure 20 and Figure 21)
MIN
MAX
UNIT
tval
tval(ptp)
ton
toff
tsu
tsu(ptp)
th
trst
trst-clk
trst-off
NOTES:
CLK to signal valid delay-bused signals (see Notes 5, 6, 7, 8)
2
11
ns
CLK to signal valid delay-point-to-point (see Notes 5, 6, 7)
2
12
ns
Float-to-active delay (see Note 5)
2
ns
Active-to-float delay (see Note 5)
28
ns
Input setup time to CLK-bused signals (see Notes 7, 9)
7
ns
Input setup time to CLK-point-to-point (see Notes 7, 9)
10
ns
Input hold time from CLK (see Notes 9, 10)
3
ns
Reset active time after power stable (see Note 11)
1
ms
μ
s
ns
Reset active time after CLK stable (see Note 9)
100
Reset active to output float delay (see Notes 9, 12)
40
5. See timing measurement conditions in the Output Timing Measurement Conditions diagram of the PCI Specification 2.0.
6. Minimum times are measured with 0 pF equivalent load; maximum times are measured with 50 pF equivalent load. Actual test
capacitance can vary, but results should be correlated to these specifications.
7. REQ and GNT are point-to-point signals and have different output valid delay and input setup times, respectively, than do bused
signals. GNT has a setup time of 10 ns; REQ has an output valid delay time of 12 ns. All other signals are bused.
8. The maximum value of tval for the STOP signal is 12 ns. PCI Specification Revision 2.0 defines a maximum value of 11 ns. No
system-related problems have been attributed to this exception to electrical timing defined in the PCI Specification.
9. See timing measurement conditions in the Input Timing Measurement Conditions diagram of the PCI Specification 2.0.
10. The minimum hold time for all TI380PCIA inputs is 3 ns. PCI Specification Revision 2.0 defines a minimum input hold time of 0 ns.
No system-related problems have been attributed to this exception to electrical timing defined in the PCI Specification.
11. RST is asserted and deasserted asynchronously with respect to CLK. Refer to PCI Specifications 2.0 for more information.
12. All output drivers must be floated when RST is active.
A
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