參數(shù)資料
型號(hào)： TI380PCM
廠商： Texas Instruments, Inc.
英文描述： PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
中文描述： PCI總線接口，可用于TI380 COMMPROCESSORS
文件頁數(shù)： 20/40頁
文件大小： 530K
代理商： TI380PCM
TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS035 – JUNE 1997
20
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
FIFO operation (read cycles) (continued)
bytes received from the PCI bus and decrements its DMA length counter. If the DMA count is not zero, but the
TI380C2x
releases the SIF bus, the TI380PCIA continues to read data from the PCI bus. The TI380PCIA logic
terminates the PCI ownership when the DMA count goes to zero.
The TI380PCIA always performs memory-read line commands on the PCI bus regardless of DMA count or
address alignment.
BIA interface
On power up, BIA data is loaded from the EEPROM and held in registers inside the TI380PCIA. All the pins on
the local bus of the TI380C2x
necessary to sense an access from the TI380C2x
to an attached BIA ROM are
connected to the TI380PCIA. When the TI380PCIA senses an access to the BIA ROM, it drives the BIA data
onto the MADHxx bus, simulating the presence of a BIA ROM on the TI380C2x
local bus.
TI380PCIA registers
The TI380PCIA supports a number of registers to facilitate communications between the host computer and
the token-ring LAN subsystem. It also performs address translation to map TI380C2x
DIO registers into host
computer memory or I/O space. Table 4 lists the configuration space registers implemented within the
TI380PCIA.
Table 4. Configuration Space Header
DWORD ADDRESS
BYTE 3
BYTE 2
BYTE 1
BYTE 0
READ/WRITE
0x00
Device ID
Vendor ID
R
0x04
Status
Command
R/W
0x08
Class Code
Revision ID
R
0x0C
Built-In Self-Test
Header Type
Latency Timer
Cache Line Size
R/W
0x10
Base Address I/O
R/W
0x14
Base Address Memory
R/W
0x18
Reserved (returns 0)
R
0x1C
Reserved (returns 0)
R
0x20
Reserved (returns 0)
R
0x24
Reserved (returns 0)
R
0x28
Reserved (returns 0)
R
0x2C
Reserved (returns 0)
R
0x30
Expansion ROM Base Address
R/W
0x34
Reserved (returns 0)
R
0x38
Reserved (returns 0)
R
0x3C
Max_Lat
Min_Gnt
Interrupt Pin
Interrupt Line
R/W
0x40
Miscellaneous Control (MISCCTRL) Register
R/W
0x44
Board Configuration Register
R
0x48
Reserved (returns 0)
EEPROM
R/W
0x4C
Hardwired DEVICE ID
Hardwired VENDOR ID
R
0x50
H/W Sub
class
H/W Max Lat
H/W Min_Gnt
H/W Revision ID
R
0x54
TI380PCIA Interface Control Register
R
0x58–0xFF
Reserved (returns 0 when read)
Shading denotes registers that are autoloaded from an external serial EEPROM at power up.
A
TI380C3x devices can be used with TI380PCIA in the same way as TI380C2x devices.
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