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參數(shù)資料
| 型號： | TI380PCM |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS |
| 中文描述： | PCI總線接口，可用于TI380 COMMPROCESSORS |
| 文件頁數(shù)： | 18/40頁 |
| 文件大小： | 530K |
| 代理商： | TI380PCM |
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TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS035 – JUNE 1997
18
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
in-circuit test NAND tree operation (continued)
SADL7
0
SADL6
0
SADL5
0
SADL4
0
SADL3
0
SADL2
0
SADL1
1
SADL0
0
Figure 6. SADL0–SADL7 Pins for Activation of NAND Tree
SADL7
SADL6
SADL5
SADL4
SADL3
SADL2
SADL1
SADL0
0
0
0
0
0
0
0
0
Figure 7. SADL0–SADL7 Pins for Deactivation of NAND Tree
TI380PCIA device operation
The TI380PCIA PCIIF functions as both master and slave of the PCI bus.
TI380PCIA behavior as a PCI bus target
The PCIIF in the TI380PCIA acts as an I/O slave to the PCI bus after power up and when the LAN subsystem
is not the PCI bus master. It monitors and decodes PCI commands for memory, I/O, and configuration accesses.
Enabling of memory and I/O accesses are performed by setting and clearing bits in the command register.
TI380PCIA behavior as a PCI bus master
The TI380PCIA requests that it become a master on the PCI bus after the TI380C2x
initiates a DMA transfer
to the TI380PCIA. The TI380C2x
begins a DMA series by asserting SBRQ and requesting its own system
interface bus. The TI380PCIA performs a DIO access to the TI380C2x
and reads the DMA length before
granting the SIF bus to the TI380C2x
. (The read cycle occurs only on the first transaction of the DMA access.)
If the TI380C2x
has requested DMA write access and there is no DIO access from the PCI bus pending, the
TI380PCIA acknowledges the request and latches the DMA address and completes the write cycle from the
TI380C2x
to start filling the FIFO. Subsequent writes continue to fill the FIFO. When the FIFO contains the
smaller of 60 bytes or one cache line of data, the PCIIF logic arbitrates for the PCI bus and transfers the data
in a burst sequence.
If the access is a read access, the TI380PCIA acknowledges the request and latches the DMA address. It then
initiates a read access on the PCI bus. If the DMA length exceeds the cache line size,
as defined by the contents
of the TI380PCIA cache line size configuration register, then the read access on the PCI bus is a burst read.
As data is available from the PCI bus, it is provided to the TI380C2x
. Since the PCI bus has a higher bandwidth
than the TI380C2x
SIF bus, the 64-byte FIFO in the TI380PCIA fills as the burst read continues. If the FIFO
fills before the DMA length is reached, the PCI master relinquishes the bus until the FIFO is almost empty.
If a DIO conflict occurs while the DMA is in progress, the TI380PCIA forces the TI380C2x
off the SIF bus to
allow the DIO to complete. The DMA operation resumes at the point where it was interrupted and continues until
completion.
removal of TI380PCIA as bus master
The TI380PCIA is removed as the PCI bus master under two conditions:
Target-initiated retry and/or termination
Master-initiated termination as no PCI agent asserted DEVSEL
TI380PCIA behavior on the SIF bus
The TI380PCIA SIF functions as both master and slave of the SIF bus.
A
TI380C3x devices can be used with TI380PCIA in the same way as TI380C2x devices.
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