參數(shù)資料
型號(hào)： TI380PCM
廠商： Texas Instruments, Inc.
英文描述： PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
中文描述： PCI總線接口，可用于TI380 COMMPROCESSORS
文件頁(yè)數(shù)： 5/40頁(yè)
文件大?。?/td> 530K
代理商： TI380PCM
TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS035 – JUNE 1997
5
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Terminal Functions (Continued)
TERMINAL
NAME
DESCRIPTION
I/O
NO.
VDD
10
22
34
37
46
50
58
70
79
82
94
106
118
130
142
I
5-V supply. These pins must be attached to the common system power supply plane.
SYSTEM INTERFACE (SIF)
SADH0/ROMA08
SADH1/ROMA09
SADH2/ROMA10
SADH3/ROMA11
SADH4/ROMA12
SADH5/ROMA13
SADH6/ROMA14
SADH7/ROMA15
113
114
115
116
117
119
120
121
I/O
System address/data bus—high byte. These lines make up the most significant byte (MSByte) of each
TI380C2x§ address word (32-bit address bus) and data word (16-bit data bus). The most significant bit
(MSB) is SADH0, and the least significant bit (LSB) is SADH7.
Address-multiplexing bits 31–24 and bits 15–8
Data-multiplexing bits 15–8
During accesses to the ROM address space from the PCI bus, these lines provide the eight most
significant address bits to the ROM.
SADL0/ROMD7
SADL1/ROMD6
SADL2/ROMD5
SADL3/ROMD4
SADL4/ROMD3
SADL5/ROMD2
SADL6/ROMD1
SADL7/ROMD0
132
133
134
135
137
138
139
140
I/O
System address/data bus—low byte. These lines make up the least significant byte (LSByte) of each
address word (32-bit address bus) and data word (16-bit data bus). The MSB is SADL0, and the LSB
is SADL7. These address lines also make up the ROM address.
Address-multiplexing bits 23–16 and bits 7–0
Data-multiplexing bits 7–0
During accesses to the ROM address space from the PCI bus, these lines transfer data from the ROM
to the TI380PCIA.
SALE
143
I
System-address latch-enable. SALE is the enable pulse used to latch the 16 LSBs of the address
externally from the SADH0–SADH7 and SADL0–SADL7 buses at the start of the DMA cycle.
SAS
2
I/O
System-memory address strobe. SAS is an active-low address strobe that is an output during DIO and
an input during DMA.#
H =
L
SIF bus clock. The TI380C2x§ requires SBCLK to synchronize its bus timings for all DMA transfers
(see Note 1).
Address not valid
Address is valid and a transfer operation is in progress
=
SBCLK
141
O
I = in, O = out
The TI380PCIA SIF pin names correspond to a subset of the system interface pins on a TI380C2x§. See the TI380C2x§ data sheets for more
information on individual pins. Like-named pins on the TI380PCIA and TI380C2x§ system interfaces are intended to be connected to each
other.
§TI380C3x devices can be used with TI380PCIA in the same way as TI380C2x devices.
Typical bit-ordering for Intel
and Motorola
processor buses
#The signal connecting this pin to the TI380C2x§ also should be connected to a 4.7-k
pullup resistor.
||The TI380PCIA BIF pin names correspond to a subset of the local memory bus interface pins on a TI380C2x§. Like-named pins on the two
devices are intended to be connected to each other. Consult the TI380C2x§ data sheets for more information on individual pins.
NOTE 1: The TI380PCIA allows driver software to set SBCLK output to a steady high state. This signal is driven to a steady high state during
power-down operations.
A
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