參數(shù)資料
型號(hào)： TI380PCM
廠商： Texas Instruments, Inc.
英文描述： PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
中文描述： PCI總線接口，可用于TI380 COMMPROCESSORS
文件頁(yè)數(shù)： 24/40頁(yè)
文件大?。?/td> 530K
代理商： TI380PCM
TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS035 – JUNE 1997
24
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
base address I/O register (BASE0)—configuration space DWORD address (0x10)
Figure 10 shows the I/O base address register (BASE0) layout.
Base Address
Reserved
I/O Space Indicator
0
0
31
4
3
2
1
0
1
0
0
Figure 10. Base Address Register for I/O
The TI380PCIA supports only one I/O address range decoded down to eight contiguous 32-bit locations. After
reset, the value of the address map is set to 0x1. Bits 0–4 are read-only and contain 0x1. The LAN subsystem
is expected to reside in I/O space under normal operations for conformance with the TI2000 software
specification.
base address memory register (BASE1)—configuration space DWORD address (0x14)
Figure 11 shows the memory base address register (BASE1) layout.
Base Address
Prefetchable
Type
Memory Space Indicator
0
31
4
3
2
1
0
0
0
0
0
Figure 11. Base Address Register for Memory
The TI380PCIA supports only one memory address range decoded down to eight contiguous 32-bit locations.
After reset, the value of the address map is set to 0x0. Bits 0–4 are read-only and contain 0x0. The LAN
subsystem is expected to reside in I/O space under normal operations for conformance with the TI2000
software specification; therefore, this register is not used.
expansion ROM base address register (BASEROM)—configuration space DWORD address (0x30)
Figure 12 shows the layout of the expansion ROM base address register.
Expansion ROM Base Address
(Upper 21 Bits)
Reserved
Address Decode Enable
1
10
11
31
0
Figure 12. Expansion ROM Base Address Register Layout
The TI380PCIA supports an RPL expansion ROM on a PCI bus add-in card. This register is used to configure
the location of the expansion ROM. The BASEROM supports address alignment on a 64K-byte boundary.
Bits 16–31 and bit 0 of BASEROM are read/write. Bits 1–15 are read-only and are read as 0x0. Bit 0 is set by
the host. The TI380PCIA supports 64K-byte ROM devices.
A
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