參數(shù)資料
型號： TI380PCM
廠商： Texas Instruments, Inc.
英文描述： PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
中文描述： PCI總線接口，可用于TI380 COMMPROCESSORS
文件頁數(shù)： 2/40頁
文件大?。?/td> 530K
代理商： TI380PCM
TI380PCIA
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS035 – JUNE 1997
2
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
pin assignments
The pin assignments for the TI380PCIA (144-pin plastic quad flat package) are shown below.
S
S
S
PCM PACKAGE
(TOP VIEW)
S
ROMA01
ROMA02
VDD
ROMA03
ROMA04
ROMA05
ROMA06
ROMA07
GND
MADH00
MADH01
MADH02
MADH03
MADH04
VDD
MADH05
MADH06
MADH07
ROMCS
DB9/UTP
GND
AD00
AD01
AD02
AD03
AD04
VDD
AD05
AD06
VDD
AD07
C/BE0
GND
AD08
AD09
AD10
SLDS
SAS
SHALT
GND
SBGR
SIRQ
SBERR
MROMEN
MAX0
VDD
SBRLS
SCS
SRSX
SRS0
SRS1
GND
SRESET
MAX2
MBIAEN
INTA
RST
VDD
PCLK
GND
GNT
REQ
AD31
GND
AD30
AD29
GND
AD28
AD27
VDD
AD26
AD25
1
S
1
1
1
S
1
S
1
S
1
S
1
G
1
S
1
S
1
S
1
S
1
M
1
1
1
1
1
S
1
1
G
1
S
1
E
1
S
1
S
1
S
1
V
1
1
S
1
S
1
1
1
1
3
3
3
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
D
V
A
C
G
I
A
A
A
A
A
A
A
I
T
D
S
P
S
P
G
A
G
A
A
F
A
1
E
1
R
1
7
7
7
A
A
S
G
I
G
G
C
S
C
S
S
S
NOTE: Pin 1 is positioned at the upper left corner.
D
V
D
V
D
V
D
V
D
V
D
V
D
A
相關(guān)PDF資料
PDF描述
TIBPAL22V10-20MFK Adjustable 2.5-36V +/-0.4% Tolerance, 1-100mA Shunt Regulator; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Rail; Qty per Container: 98
TIBPAL22V10-20MJT HIGH-PERFORMANCE IMPACT-X E PROGRAMMABLE ARRAY LOGIC CIRCUITS
TIBPAL22V10C Adjustable 2.5-36V +/-0.4% Tolerance, 1-100mA Shunt Regulator; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Tape and Reel; Qty per Container: 2500
TIBPAL22V10AMFK HIGH-PERFORMANCE IMPACT E PROGRAMMABLE ARRAY LOGIC CIRCUITS
TIBPAL22V10CFN HIGH-PERFORMANCE IMPACT E PROGRAMMABLE ARRAY LOGIC CIRCUITS
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