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參數(shù)資料
| 型號(hào)： | ST92186B3BK |
| 廠商： | STMICROELECTRONICS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP32 |
| 封裝： | PLASTIC, SDIP-32 |
| 文件頁(yè)數(shù)： | 81/148頁(yè) |
| 文件大小： | 1664K |
| 代理商： | ST92186B3BK |
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ST92186B - DEVICE ARCHITECTURE
MMU REGISTERS (Cont’d)
2.7.2 CSR: Code Segment Register
This register selects the 64-Kbyte code segment
being used at run-time to access instructions. It
can also be used to access data if the spm instruc-
tion has been executed (or ldpp, ldpd, lddp).
Only the 6 LSBs of the CSR register are imple-
mented, and bits 6 and 7 are reserved. The CSR
register allows access to the entire memory space,
divided into 64 segments of 64 Kbytes.
To generate the 22-bit Program memory address,
the contents of the CSR register is directly used as
the 6 MSBs, and the 16-bit virtual address as the
16 LSBs.
Note: The CSR register should only be read and
not written for data operations (there are some ex-
ceptions which are documented in the following
paragraph). It is, however, modified either directly
by means of the jps and calls instructions, or
indirectly via the stack, by means of the rets in-
struction.
CODE SEGMENT REGISTER (CSR)
R244 - Read/Write
Register Page: 21
Reset value: 0000 0000 (00h)
Bits 7:6 = Reserved, keep in reset state.
Bits 5:0 = CSR_[5:0]: These bits define the 64-
Kbyte memory segment (among 64) which con-
tains the code being executed. These bits are
used as the most significant address bits (A21-16).
2.7.3 ISR: Interrupt Segment Register
INTERRUPT SEGMENT REGISTER (ISR)
R248 - Read/Write
Register Page: 21
Reset value: undefined
ISR and ENCSR bit (EMR2 register) are also de-
scribed in the chapter relating to Interrupts, please
refer to this description for further details.
Bits 7:6 = Reserved, keep in reset state.
Bits 5:0 = ISR_[5:0]: These bits define the 64-
Kbyte memory segment (among 64) which con-
tains the interrupt vector table and the code for in-
terrupt service routines. These bits are used as the
most significant address bits (A21-16). The ISR is
used to extend the address space whenever an in-
terrupt occurs: ISR points to the 64-Kbyte memory
segment containing the interrupt vector table and
the interrupt service routine code. See also the In-
terrupts chapter.
70
00
CSR_5
CSR_4
CSR_3
CSR_2
CSR_1
CSR_0
70
0
ISR_5
ISR_4
ISR_3
ISR_2 ISR_1 ISR_0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST92195B2T1/XXX | 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP64 |
| ST92195B3B1/XXX | 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP56 |
| ST92195B4B1/XXX | 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP56 |
| ST92195B5T1/XXX | 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP64 |
| ST92195B6T1/XXX | 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST92195 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:32-64K ROM HCMOS MCU WITH ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER |
| ST92195B | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:32-64K ROM HCMOS MCU WITH ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER |
| ST92195B1 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:32-64K ROM HCMOS MCU WITH ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER |
| ST92195B1B1 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:32-64K ROM HCMOS MCU WITH ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER |
| ST92195B1T1 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:32-64K ROM HCMOS MCU WITH ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER |
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