參數(shù)資料
型號： ST92186B3BK
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP32
封裝： PLASTIC, SDIP-32
文件頁數(shù)： 101/148頁
文件大?。?/td> 1664K
代理商： ST92186B3BK
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ST92186B - RESET AND CLOCK CONTROL UNIT (RCCU)
4 RESET AND CLOCK CONTROL UNIT (RCCU)
4.1 INTRODUCTION
The Reset and Clock Control Unit (RCCU) com-
prises two distinct sections:
– the Clock Control Unit, which generates and
manages the internal clock signals.
– the Reset/Stop Manager, which detects and
flags Hardware, Software and Watchdog gener-
ated resets.
4.2 CLOCK CONTROL REGISTERS
MODE REGISTER (MODER)
R235 - Read/Write
System Register
Reset Value: 1110 0000 (E0h)
*Note:
This register contains bits which relate to
other functions; these are described in the chapter
dealing with Device Architecture. Only those bits
relating to Clock functions are described here.
Bit 5 = DIV2:
OSCIN Divided by 2.
This bit controls the divide by 2 circuit which oper-
ates on the OSCIN Clock.
0: No division of the OSCIN Clock
1: OSCIN clock is internally divided by 2
Bits 4:2 = PRS[2:0]:
Clock Prescaling.
These bits define the prescaler value used to pres-
cale CPUCLK from INTCLK. When these three
bits are reset, the CPUCLK is not prescaled, and is
equal to INTCLK; in all other cases, the internal
clock is prescaled by the value of these three bits
plus one.
CLOCK CONTROL REGISTER (CLKCTL)
R240 - Read Write
Register Page: 55
Reset Value: 0000 0000 (00h)
Bits 7:4 = Reserved.
Must be kept reset for normal operation.
Bit 3 = SRESEN:
Software Reset Enable.
0: The HALT instruction turns off the quartz, the
PLL and the CCU
1: A Reset is generated when HALT is executed
Bits 2:0 = Reserved.
Must be kept reset for normal operation.
CLOCK FLAG REGISTER (CLK_FLAG)
R242 -Read/Write
Register Page: 55
Reset Value: 0100 1000 after a Watchdog Reset
Reset Value: 0010 1000 after a Software Reset
Reset Value: 0000 1000 after a Power-On Reset
Warning: If this register is accessed with a logical
instruction, such as AND or OR, some bits may not
be set as expected.
Bit 7 = Reserved.
Must be kept reset for normal operation.
Bit 6 = WDGRES:
Watchdog reset flag.
This bit is read only.
0: No Watchdog reset occurred
1: Watchdog reset occurred
Bit 5 = SOFTRES:
Software Reset Flag.
This bit is read only.
0: No software reset occurred
1: Software reset occurred (HALT instruction)
Bits 4:0 = Reserved.
Must be kept reset for normal operation.
70
-
DIV2
PRS2
PRS1
PRS0
-
70
-
SRESEN
-
70
-
WDG
RES
SOFT
RES
--
-
相關(guān)PDF資料
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