- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98146 > ST92186B3BK (STMICROELECTRONICS) 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP32 PDF資料下載
參數(shù)資料
| 型號： | ST92186B3BK |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP32 |
| 封裝： | PLASTIC, SDIP-32 |
| 文件頁數(shù)： | 126/148頁 |
| 文件大?。?/td> | 1664K |
| 代理商： | ST92186B3BK |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁當前第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁
Obsolete
Product(s)
- Obsolete
Product(s)
Obsolete
Product(s)
- Obsolete
Product(s)
79/148
ST92186B - OSDRAM CONTROLLER
OSDRAM CONTROLLER (Cont’d)
7.3.2.1 Time Sharing during Display
The time necessary to display a character on the
screen defines the basic repetitive cycle of the OS-
DRAM controller. This whole cycle represents
therefore 18 clock periods. This cycle is divided in
9 sub-cycles called “slots”. Each slot is allocated in
real-time either to the CPU or the Display:
– In single mode, this 9-slot cycle is repeated con-
tinuously providing only CPU slots (single cycle),
until the OSDRAM controller is switched off by
the main program execution.
– In shared mode, this 9-slot cycle provides Dis-
play slots followed by CPU slots.
Each slot represents a two-byte exchange (read or
write) between the OSDRAM memory and the oth-
er units:
Display Reading slot (DIS): 16 bits are read from
the OSDRAM and sent to the display unit, the ad-
dress being defined by the display address gener-
ator.
Direct CPU Access slot (CPU): 16 bits are ex-
changed (read or write) between the OSDRAM
and its controller but only 8 bits are exchanged
with the CPU, the address being defined by the
CPU memory address bus.
Figure 44. Time sharing during display
Display reading is handled as follows:
– DIS(1) & DIS(2) are dedicated to reading the
character code, its parallel attributes & associat-
ed palette pointer.
– DIS(3) provides the foreground palette.
– DIS(4) provides the background palette. In case
of Underline activation (refer to the OSD control-
ler paragraph for more details), the DIS(4) slot is
no longer provides the background palette con-
tent (useless information) but recovers the Un-
derline color set data.
The CPU write accesses are handled as follows:
Because of the 16-bit word width inside the OS-
DRAM matrix, it is obviously necessary to perform
a CPU write access in 2 steps:
– Reading the OSDRAM word
– Rewriting it with the same values except for the
8 modified bits.
Each time a CPU write operation is started, the
next following CPU slot will be used as a read slot,
the effective write to the OSDRAM being complet-
ed at the next CPU slot.
7.3.2.2 Time sharing within the TV line
At the beginning of each TV line, the OSDRAM is
accessed (read) by the Display controller in order
to get all the row attributes. When the TV line is
recognized as the one where data have to be dis-
played, the Shared cycle is activated at the time
the data has to be processed for display.
CPU
(R/W)
CPU
(R/W)
CPU
(R/W)
CPU
(R/W)
CPU
(R/W)
CPU
(R/W)
CPU
(R/W)
CPU
(R/W)
CPU
(R/W)
CPU
(R/W)
DIS
(1)
CPU
(R/W)
DIS
(2)
CPU
(R/W)
DIS
(3)
CPU
(R/W)
DIS
(4)
CPU
(R/W)
Shared Cycle
Single Cycle
One Character Display Time
相關PDF資料 |
PDF描述 |
|---|---|
| ST92195B2T1/XXX | 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP64 |
| ST92195B3B1/XXX | 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP56 |
| ST92195B4B1/XXX | 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP56 |
| ST92195B5T1/XXX | 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP64 |
| ST92195B6T1/XXX | 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP64 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ST92195 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32-64K ROM HCMOS MCU WITH ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER |
| ST92195B | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32-64K ROM HCMOS MCU WITH ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER |
| ST92195B1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32-64K ROM HCMOS MCU WITH ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER |
| ST92195B1B1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32-64K ROM HCMOS MCU WITH ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER |
| ST92195B1T1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32-64K ROM HCMOS MCU WITH ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER |
發(fā)布緊急采購，3分鐘左右您將得到回復。