參數(shù)資料
型號： ST92186B3BK
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP32
封裝： PLASTIC, SDIP-32
文件頁數(shù)： 20/148頁
文件大?。?/td> 1664K
代理商： ST92186B3BK
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ST92186B - ON SCREEN DISPLAY CONTROLLER (OSD)
OSD CONTROLLER (Cont’d)
ENABLE REGISTER (OSDER)
R248 - Read/Write
Register Page: 42
Reset Value: 0000 0000 (00h)
Bit 7 = DION
Display ON
This bit is used in combination with the OSDE bit
to control the display working mode. See Table 25.
Warning: after a reset, a valid HSYNC signal is re-
quired to write to the OSDRAM, whatever the
clock rate (CPU or Pixel clock rate).
Bit 6 = OSDE
OSD Enable
This bit is used in combination with the DION bit to
control the display working mode. See Table 18.
Note 1: When the (DION,OSDE) bits switch from
any other value to (1,1), i.e. when the controller is
switched to a full OSD function, the “first buffer
start address” content is used to locate the first
Row buffer to process.
While the full Display function is running, the DION
& OSDE bits remain set and the first buffer start
address is not used again, even if both bits are re-
written to “1”.
Note 2: It is strongly recommended to use state 3
only if the OSDRAM has been initialized using
state 2.
Warning 1: States 3 and 4 (refer to Table 25) can
only be used if HSYNC and VSYNC are applied on
the external pins.
Warning 2: After a reset, a valid HSYNC signal is
required to write to the OSDRAM, regardless of
the clock rate (CPU or Pixel clock rate).
Warning 3: When the OSD is displayed, it is ad-
vised not to write to the OSDRAM when a VSYNC
pulse occurs. In Normal operating mode, this con-
figration will never happen.
Bit 5 = TE
Transfer Enable bit
This bit controls the “swap to next row buffer” func-
tion whenever the Scan Line counter content
matches the Event Line parameter value.
An interrupt request pulse is generated and for-
warded to the core each time the match occurs re-
gardless of the value of TE.
0: Row buffer swap disabled. The current row buff-
er content is simply ignored and the screen will
display the border color, as if the current buffer
content was already processed.
1: A Row buffer swap enabled
Note: Refer to Section 7.4.7.8 for more details
about using the TE bit.
Bit 4 = DBLS
Double Scan bit
This bit defines if the display works in 1H or 2H
mode.
0: The display works in “single scan” or “1H” mode.
1: The display works in “double scan” or “2H”
mode. The 2H mode is used in progressive scan
display (60Hz field, 525 lines).
Note: the DBLS bit acts on the display vertical de-
lay for field determination (refer to the VD[3:0] bits
of the Delay register OSDDR).
The DBLS bit also acts on the Line Start Mute (re-
fer to the LSM[2:0] bits of the Mute register OSD-
MR) and the HSY flag bit.
Bit 3 = NIDS
Non Interlaced Display control bit
This bit selects Interlaced or Non-Interlaced mode.
0: The display works in interlaced mode (line
counting, fringe and rounding algorithms are 2-
field based)
1: The display works in non-interlaced mode (line
counting, fringe and rounding algorithms are 1-
field based).
Bit 2 = TSLE
Translucency Enable bit
This bit enables or disables the digital translucen-
cy signal (TSLU) generation. (Refer to Section
7.4.3.11).
0: The TSLU signal built by the Display controller
remains continuously idle regardless of OSD ac-
tivity.
1: The TSLU signal carries the real time back-
ground information and can be output through
the I/O pin alternate function.
Bit 1 = Reserved. Must be kept at reset.
Bit 0 = FPIXC
Fast Pixel Clock control bit
This bit handles the divide-by-2 prescaler inserted
between the Skew Corrector output and the Dis-
play Pixel clock input.
0: The Skew corrector clock output is divided by 2
to provide the Pixel clock.
1: The Skew corrector clock output is directly tak-
en as the Pixel Clock.
70
DION
OSDE
TE
DBLS
NIDS
TSLE
-
FPIXC
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