參數資料
型號： ST92186B3BK
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP32
封裝： PLASTIC, SDIP-32
文件頁數： 39/148頁
文件大?。?/td> 1664K
代理商： ST92186B3BK
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133/148
ST92186B - A/D CONVERTER (A/D)
7.8 A/D CONVERTER (A/D)
7.8.1 Introduction
The 8-bit Analog to Digital Converter uses a fully
differential analog configuration for the best noise
immunity and precision performance. The analog
voltage references of the converter are connected
to the internal AVDD & AVSS analog supply pins of
the chip if they are available, otherwise to the ordi-
nary VDD and VSS supply pins of the chip. The
guaranteed accuracy depends on the device (see
Electrical Characteristics). A fast Sample/Hold al-
lows quick signal sampling for minimum warping
effect and conversion error.
7.8.2 Main Features
s
8-bit resolution A/D Converter
s
Single Conversion Time (including Sampling
Time):
– 138 internal system clock periods in slow
mode (~5.6 s @25Mhz internal system
clock);
– 78 INTCLK periods in fast mode (~6.5 s @
12MHZ internal system clock)
s
Sample/Hold: Tsample=
– 84 INTCLK periods in slow mode (~3.4 s
@25Mhz internal system clock)
– 48 INTCLK periods in fast mode (~4 s
@12Mhz internal system clock)
s
Up to 5 (SDIP42) or 3 (SDIP32) Analog Inputs
s
Single/Continuous Conversion Mode
s
External
source
Trigger
(Alternate
synchronization)
s
Power Down mode (Zero Power Consumption)
s
1 Control Logic Register
s
1 Data Register
7.8.3 General Description
Depending on device, up to 5 (SDIP42) or 3
(SDIP32) analog inputs can be selected by soft-
ware.
Different conversion modes are provided: single,
continuous, or triggered. The continuous mode
performs a continuous conversion flow of the se-
lected channel, while in the single mode the se-
lected channel is converted once and then the log-
ic waits for a new hardware or software restart.
A data register (ADDTR) is available, mapped in
page 62, allowing data storage (in single or contin-
uous mode).
The start conversion event can be managed ei-
ther:
– by software, writing the START/STOP bit of the
Control Logic Register
– or by hardware using an external signal on the
EXTRG triggered input (negative edge sensitive)
connected as an Alternate Function to an I/O port
bit.
Figure 66. A/D Converter Block Diagram
n
ST
9
BU
S
SUCCESSIVE
APPROXIMATION
REGISTER
ANALOG
MUX
DATA
REGISTER
CONTROL LOGIC
S/H
Ain1
Ainx
Ain0
EXTRG
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