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參數(shù)資料
| 型號： | ST92186B3BK |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP32 |
| 封裝： | PLASTIC, SDIP-32 |
| 文件頁數(shù)： | 22/148頁 |
| 文件大小： | 1664K |
| 代理商： | ST92186B3BK |
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ST92186B - ON SCREEN DISPLAY CONTROLLER (OSD)
OSD CONTROLLER (Cont’d)
DELAY REGISTER (OSDDR)
R249 - Read/Write
Register Page: 42
Reset Value: 0xxx xxxx
Note: The display may flicker if you write to the
Delay Register while OSD is fully on.
Bit 7 = PASW
Palette Swap bit
The PASW bit is used in serial or basic parallel
modes to provide access to the extended palettes.
It is still active when you work in extended parallel
mode, however it not needed as the FXP and BXP
bits are available (refer to Section 7.4.7.7).
0: The basic palette sets are used.
1: The extended palette sets are used.
Bit 6 = HPOL
Hsync signal Polarity selection bit
This bit has to be configured according to the po-
larity of the Hsync input signal.
0: Hsync input pulses are of positive polarity
1: Hsync input pulses are of negative polarity
Bit 5 = VPOL
Vsync signal POLarity selection bit
This bit has to be configured according to the po-
larity of the Vsync input signal.
0: Vsync input pulses are of positive polarity
1: Vsync input pulses are of negative polarity
Bit 4 = FBPOL
Fast Blanking signal Polarity selec-
tion bit
This bit selects the polarity of the Fast Blanking
(FB) output signal.
0: FB output pulses are of positive polarity (FB ac-
tive high)
1: FB output pulses are of negative polarity (FB ac-
tive low)
Note: the FB signal is kept active during the
VSYNC vertical retrace.
Bits 3:0 = VD[3:0]
Vertical Delay control bits
This 4-bit value is used to program an internal de-
lay on vertical sync pulses applied to VSYNC input
pin.
The purpose of the programmable delay is to pre-
vent vertical OSD jitter in case the rising edge of
external vertical sync pulse coincides with thatofan
external horizontal sync pulse.
The delay applied is expressed by the following
equations (4 MHz is the frequency issued directly
from the crystal oscillator):
for 2H display mode:
[VD[3:0]+1] * 8*(1/4MHz) =< d =< [VD[3:0]+2] *
8*(1/4MHz)
for 1H display mode:
[VD[3:0]+1] *16*(1/4MHz) =< d =< [VD[3:0]+2]
*16*(1/4MHz)
Note: programming the Vertical Delay to Fh will
freeze the scan line counter disabling any further
RGB output.
Note: It is mandatory for the CPU to initialize the
Vertical Delay Register to avoid any problems.
SCAN LINE REGISTER (OSDSLR)
R251 - Read Only
Register Page: 42
Reset Value: xxxx xxxx (xxh)
Bits 7:0 = SL[7:0]
Scan Line Counter Value
These bits indicate the current vertical position of
the TV beam.
The most significant bit SL8 of this counter is locat-
ed in the Flag Bit register OSDFBR (see below).
This counter starts from 0 at the top of the screen
(i.e. after the Vsync pulse) and is incremented by
HSYNC.
70
PASW HPOL
VPOL FBPOL
VD3
VD2
VD1
VD0
70
SL7
SL6
SL5
SL4
SL3
SL2
SL1
SL0
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