參數(shù)資料
型號(hào)： ST92186B3BK
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP32
封裝： PLASTIC, SDIP-32
文件頁數(shù)： 27/148頁
文件大?。?/td> 1664K
代理商： ST92186B3BK
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ST92186B - IR PREPROCESSOR (IR)
7.5 IR PREPROCESSOR (IR)
7.5.1 Functional Description
The IR Preprocessor measures the interval be-
tween adjacent edges of the demodulated output
signal from the IR amplifier/detector. You can
specify the polarity using the POSED and NEGED
bit in the IRSCR register The measurement is rep-
resented in terms of a count obtained with a
12.5KHz clock and stored in the IRPR register.
Whenever an edge of specified polarity is detect-
ed, the count accumulated since the previously
detected edge is latched into an 8-bit register and
an interrupt request IRQ is generated if the IR-
WDIS bit is reset in the IRSCR register.
Note: Any count less than 255 stored in the latch
register is over-written in case the P fails to exe-
cute the read before the next edge occurs.
In case an edge is not detected in about 20ms (the
count reaches its maximum value of 255) the
count is latched immediately and the IRQ flag is
set. An overflow flag (not accessable) is also set
internally.
Each time an interrupt is received, it must be ac-
knowleged by writing any value in the IRPR regis-
ter. Otherwise no further interrupts will be generat-
ed.
Warning: The content of the latch cannot be
changed as long as the overflow flag remains set.
To clear the IRQ and internal overflow flags, just
write any value in the IRPR register. As long as the
internal overflow flag is set, no interrupt is generat-
ed.
The IR input signal is preprocessed by a spike fil-
ter. The FLSEL bit of the IRSCR register deter-
mines the width of filtered pulse.
7.5.2 Register Description
IR PULSE REGISTER (IRPR)
R248 - Read only
Register Page: 43
Reset Value: 0000 0000 (00h)
Bits 7:0 = IR[7:0]: IR pulse width in terms of
number of 12.5KHz clock cycles.
IR/SYNC CONTROL REGISTER (IRSCR)
R250 - Read/Write
Register Page: 43
Reset Value: 0000 0000 (00h)
Bits 7:6 = Reserved.
Forced by hardware to 0.
Bit 5 = Reserved.
Bit 4 = IRWDIS:
External Interrupt Source.
This bit is set and cleared by software. It selects
the source of the interrupt assigned to the external
interrupt channel. Refer to the Interrupt Chapter.
0: The interrupt request from the IR preprocessor
is forwarded to the CPU
1: The interrupt from the external interrupt pin is
forwarded to the CPU
Bit 3 = FLSEL:
Spike filter pulse width selection
This bit is set and cleared by software. It selects
the spike filter width.
0: Filter pulses narrower than 2s
1: Filter pulses narrower than 160s
Bits 2:1 = POSED, NEGED
Edge selection for the
duration measurement
Bit 0 = Reserved.
70
IR7
IR6
IR5
IR4
IR3
IR2
IR1
IR0
70
0
-
IRWDIS FLSEL POSED NEGED
-
NEGED POSED
Count latch at ...
11
Positive or negative transition of
IR or when count reaches 255
10
Negative transition of IR or when
count reaches 255
01
Positive transition of IR or when
count reaches 255
0
Only when count reaches 255
相關(guān)PDF資料
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