參數(shù)資料
型號： ST92186B3BK
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP32
封裝： PLASTIC, SDIP-32
文件頁數(shù)： 77/148頁
文件大小： 1664K
代理商： ST92186B3BK
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ST92186B - DEVICE ARCHITECTURE
2.5 MEMORY MANAGEMENT UNIT
The CPU Core includes a Memory Management
Unit (MMU) which must be programmed to per-
form memory accesses (even if external memory
is not used).
The MMU is controlled by 6 registers and 2 bits
(ENCSR and DPRREM) present in EMR2, which
may be written and read by the user program.
These registers are mapped within group F, Page
21 of the Register File. The 6 registers may be
sub-divided into 2 main groups: a first group of four
8-bit registers (DPR[3:0]), and a second group of
two 6-bit registers (CSR and ISR). The first group
is used to extend the address during Data Memory
access (DPR[3:0]). The second is used to manage
Program and Data Memory accesses during Code
execution (CSR) and Interrupts Service Routines
(ISR or CSR).
Figure 14. Page 21 Registers
ISR
EMR2
Reserved
CSR
DPR3
DPR2
DPR1
DPR0
R255
R254
R253
R252
R251
R250
R249
R248
R247
R246
R245
R244
R243
R242
R241
R240
FFh
FEh
FDh
FCh
FBh
FAh
F9h
F8h
F7h
F6h
F5h
F4h
F3h
F2h
F1h
F0h
MMU
EM
Page 21
MMU
Bit DPRREM=0
SSPLR
SSPHR
USPLR
USPHR
MODER
PPR
RP1
RP0
FLAGR
CICR
P5DR
P4DR
P3DR
P2DR
P1DR
P0DR
Reserved
ISR
EMR2
Reserved
CSR
DPR3
DPR2
1
DPR0
Bit DPRREM=1
SSPLR
SSPHR
USPLR
USPHR
MODER
PPR
RP1
RP0
FLAGR
CICR
P5DR
P4DR
P3DR
P2DR
P1DR
P0DR
Reserved
ISR
EMR2
Reserved
CSR
DPR3
DPR2
DPR1
DPR0
Relocation of P[3:0] and DPR[3:0] Registers
(default setting)
Reserved
相關(guān)PDF資料
PDF描述
ST92195B2T1/XXX 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP64
ST92195B3B1/XXX 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP56
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