參數(shù)資料
型號： ST92186B3BK
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP32
封裝： PLASTIC, SDIP-32
文件頁數(shù)： 125/148頁
文件大?。?/td> 1664K
代理商： ST92186B3BK
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ST92186B - OSDRAM CONTROLLER
7.3 OSDRAM CONTROLLER
7.3.1 Introduction
The OSDRAM Controller handles the interface be-
tween the Display Controller, the CPU and the OS-
DRAM.
The time slots are allocated to each unit in order to
optimize the response time.
The main features of the OSDRAM Controller are
the following:
s
Memory mapped in Memory Space (segment
22h of the MMU)
s
DMA access for Display control
s
Direct CPU access
7.3.2 Functional Description
The OSDRAM controller manages the data flows
between the different sub-units (display controller,
CPU) and the OSDRAM. A specific set of buses
(16-bit data, 9-bit addresses) is dedicated to these
data flows. The OSDRAM controller accesses
these buses in real time. The OSDRAM controller
has registers mapped in the ST9 register file.
As this OSDRAM controller has also to deal with
TV real time signals (On-Screen-Display), a spe-
cific controller manages all exchanges:
– Its timing generator uses the same frequency
generator as the Display (Pixel frequency multi-
plier),
– Its controller can work in two TV modes:
– Single mode: all time slots are dedicated to
the CPU.
– Shared mode: time slots are shared between
the CPU and the Display. The shared mode is
controlled by the Display controller.
– Its architecture gives priority to the TV real time
constraints: whenever there is access contention
between the CPU and the Display (shared
mode), the CPU is automatically forced in a
“wait” configuration until its request is served.
– Its controller enables a third operating mode
(stand-alone mode) which allows the application
to access the OSDRAM while the Display is
turned off. In this case, the OSDRAM controller
uses the CPU main clock.
Figure 43. Display Architecture Overview
4 * 3 BITS
DISPLAY CONTROLLER
OSDRAM CONTROLLER
OSD DISPLAY RAM
CPU INTERFACE
ROM FONT
MATRIX
REGISTER BUSES
MEMORY BUSES
ADDRESS (6+4 BITS)
OSD ADDRESS (9 BITS)
OSD DATA
(16 BITS)
RGB
FB
TRANSLUCENCY
TSLU
DATA (8 BITS)
ADDRESS (22 BITS)
DATA (8 BITS)
相關(guān)PDF資料
PDF描述
ST92195B2T1/XXX 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP64
ST92195B3B1/XXX 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP56
ST92195B4B1/XXX 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP56
ST92195B5T1/XXX 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP64
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參數(shù)描述
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ST92195B 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32-64K ROM HCMOS MCU WITH ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER
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