參數資料
型號： ST92186B3BK
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP32
封裝： PLASTIC, SDIP-32
文件頁數： 38/148頁
文件大?。?/td> 1664K
代理商： ST92186B3BK
Obsolete
Product(s)
- Obsolete
Product(s)
Obsolete
Product(s)
- Obsolete
Product(s)
132/148
ST92186B - PWM GENERATOR
PWM GENERATOR (Cont’d)
OUTPUT COMPLEMENT REGISTER (OCPL)
R251- Read/Write
Register Page 59
Reset Value: 0000 0000 (00h)
This register allows the PWM output level to be
complemented on an individual bit basis.
In default mode (reset configuration), each com-
parison true between a Compare register and the
counter has the effect of setting the corresponding
output.
At counter clear (either by autoclear comparison
true, software clear or overflow when in free run-
ning mode), all the outputs are cleared.
By setting each individual bit (OCPL.x) in this reg-
ister, the logic value of the corresponding output
will be inverted (i.e. reset on comparison true and
set on counter clear).
Example: When set to “1”, the OCPL.1 bit comple-
ments the PWM output 1.
Bit 7 = OCPL.7:
Complement PWM Output 7.
Bit 6 = OCPL.6:
Complement PWM Output 6.
Bits 5:4 = Reserved.
Must be kept in reset state.
Bit 3 = OCPL.31):
Complement PWM Output 3.
Bit 2 = OCPL.21):
Complement PWM Output 2.
Bit 1 = OCPL.1:
Complement PWM Output 1.
Bit 0 = OCPL.0:
Complement PWM Output 0.
Note 1: available on SDIP42 only.
On SDIP32, these bits are reserved and must be
kept reset.
OUTPUT ENABLE REGISTER (OER)
R252 - Read/Write
Register Page: 59
Reset Value: 0000 0000 (00h)
These bits are set and cleared by software.
0: Force the corresponding PWM output to logic
level 1. This allows the port pins to be used for
normal I/O functions or other alternate functions
(if available).
1: Enable the corresponding PWM output.
Example: Writing 03h into the OE Register will en-
able only PWM outputs 0 and 1, while outputs 2, 3,
4, 5, 6 and 7 will be forced to logic level “1”.
Bit 7 = OE.7:
Output Enable PWM Output 7.
Bit 6 = OE.6:
Output Enable PWM Output 6.
Bits 5:4 = Reserved.
Must be kept in reset state.
Bit 3 = OE.31):
Output Enable PWM Output 3.
Bit 2 = OE.21):
Output Enable PWM Output 2.
Bit 1 = OE.1:
Output Enable PWM Output 1.
Bit 0 = OE.0:
Output Enable PWM Output 0.
Note 1: available on SDIP42 only.
On SDIP32, these bits are reserved and must be
kept reset.
70
OCPL.7 OCPL.6
-
OCPL.3 OCPL.2 OCPL.1OCPL.0
70
OE.7 OE.6
-
OE.3 OE.2 OE.1 OE.0
相關PDF資料
PDF描述
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