參數(shù)資料
型號： ST7FLU05MAE
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO8
封裝： 0.150 INCH, LEAD FREE, PLASTIC, SOP-8
文件頁數(shù)： 98/124頁
文件大?。?/td> 2186K
代理商： ST7FLU05MAE
Obsolete
Product(s)
- Obsolete
Product(s)
ST7LUS5, ST7LU05, ST7LU09
On-chip peripherals
75/124
PWM0 duty cycle register low (DCR0L)
PWM0 control/status register (PWM0CSR)
DCR0L
Reset value: 0000 0000 (00h)
7
654
32
10
DCR7
DCR6
DCR5
DCR4
DCR3
DCR2
DCR1
DCR0
R/W
Table 43.
DCR0 high and low register descriptions
Bits
Name
Function
15:12
-
Reserved, must be kept cleared
11:0
DCR[11:0]
PWMx duty cycle value
This 12-bit value is written by software. The high register must be written first.
In PWM mode (OE0 = 1 in the PWMCR register) the DCR[11:0] bits define the
duty cycle of the PWM0 output signal (see Figure 41). In output compare
mode, (OE0 = 0 in the PWMCR register) they define the value to be compared
with the 12-bit upcounter value.
PWM0CSR
Reset value: 0000 0000 (00h)
7
654
32
10
Reserved
OP0
CMPF0
-R/W
R/W
Table 44.
PWM0CSR register description
Bit
Name
Function
7:2
-
Reserved, must be kept cleared.
1OP0
PWM0 output polarity
This bit is read/write by software and cleared by hardware after a reset. This bit
selects the polarity of the PWM0 signal.
0: The PWM0 signal is not inverted.
1: The PWM0 signal is inverted.
0CMPF0
PWM0 compare flag
This bit is set by hardware and cleared by software by reading the PWM0CSR
register. It indicates that the upcounter value matches the DCR0 register value.
0: Upcounter value does not match DCR value
1: Upcounter value matches DCR value
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