參數(shù)資料
型號(hào): ST7FLU05MAE
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO8
封裝: 0.150 INCH, LEAD FREE, PLASTIC, SOP-8
文件頁(yè)數(shù): 74/124頁(yè)
文件大小: 2186K
代理商: ST7FLU05MAE
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Obsolete
Product(s)
- Obsolete
Product(s)
ST7LUS5, ST7LU05, ST7LU09
Power saving modes
53/124
As soon as halt mode is entered, and if the AWUEN bit has been set in the AWUCSR
register, the AWU RC oscillator provides a clock signal (fAWU_RC). Its frequency is divided by
a fixed divider and a programmable prescaler controlled by the AWUPR register. The output
of this prescaler provides the delay time. When the delay has elapsed, the following actions
are performed:
The AWUF flag is set by hardware,
an interrupt wakes up the MCU from halt mode,
The main oscillator is immediately turned on and the 64 CPU cycle delay is used to
stabilize it.
After this start-up delay, the CPU resumes operation by servicing the AWUFH interrupt. The
AWU flag and its associated interrupt are cleared by software reading the AWUCSR
register.
To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated
by measuring the clock frequency fAWU_RC and then calculating the right prescaler value.
Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in run
mode. This connects fAWU_RC to the input capture of the 8-bit lite timer, allowing the
fAWU_RC to be measured using the main oscillator clock as a reference timebase.
The following AWUFH mode behavior is the same as normal halt mode:
The MCU can exit AWUFH mode by means of any interrupt with exit from halt capability
or a reset (see Section 8.4: Active halt and halt modes).
When entering AWUFH mode, the I bit in the CC register is forced to 0 to enable
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In AWUFH mode, the main oscillator is turned off causing all internal processing to be
stopped, including the operation of the on-chip peripherals. None of the peripherals are
clocked except those which get their clock supply from another clock generator (such
as an external or auxiliary oscillator like the AWU oscillator).
The compatibility of watchdog operation with AWUFH mode is configured by the
WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction
when executed while the watchdog system is enabled, can generate a watchdog reset.
Figure 25.
AWUF halt timing diagram
AWUFH interrupt
fCPU
Run mode
Halt mode
64 tCPU
Run mode
fAWU_RC
Clear
by software
tAWU
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