參數(shù)資料
型號: ST7FLU05MAE
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO8
封裝: 0.150 INCH, LEAD FREE, PLASTIC, SOP-8
文件頁數(shù): 79/124頁
文件大?。?/td> 2186K
代理商: ST7FLU05MAE
Obsolete
Product(s)
- Obsolete
Product(s)
I/O ports
ST7LUS5, ST7LU05, ST7LU09
58/124
Spurious interrupts
When enabling/disabling an external interrupt by setting/resetting the related OR register bit,
a spurious interrupt is generated if the pin level is low and its edge sensitivity includes
falling/rising edge. This is due to the edge detector input which is switched to ‘1’ when the
external interrupt is disabled by the OR register.
To avoid this unwanted interrupt, a “safe” edge sensitivity (rising edge for enabling and
falling edge for disabling) has to be selected before changing the OR register bit and
configuring the appropriate sensitivity again.
Caution: In case a pin level change occurs during these operations (asynchronous signal
input), as interrupts are generated according to the current sensitivity, it is advised to disable
all interrupts before and to re-enable them after the complete previous sequence in order to
avoid an external interrupt occurring on the unwanted edge.
This corresponds to the following steps:
1.
To enable an external interrupt:
a)
set the interrupt mask with the SIM instruction (in cases where a pin level change
could occur)
b)
select rising edge
c)
enable the external interrupt through the OR register
d)
select the desired sensitivity if different from rising edge
e)
reset the interrupt mask with the RIM instruction (in cases where a pin level
change could occur)
2.
To disable an external interrupt:
a)
set the interrupt mask with the SIM instruction SIM (in cases where a pin level
change could occur)
b)
select falling edge
c)
disable the external interrupt through the OR register
d)
select rising edge
9.2.2
Output modes
The output configuration is selected by setting the corresponding DDR register bit. In this
case, writing the DR register applies this digital value to the I/O pin through the latch. Then
reading the DR register returns the previously stored value.
Two different output modes can be selected by software through the OR register: Output
push-pull and open-drain.
Note:
When switching from input to output mode, the DR register has to be written first to drive the
correct level on the pin as soon as the port is configured as an output.
Table 26.
I/O output mode selection
DR
Push-pull
Open-drain
0VSS
VSS
1VDD
Floating
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