參數(shù)資料
型號： ST7FLU05MAE
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO8
封裝： 0.150 INCH, LEAD FREE, PLASTIC, SOP-8
文件頁數(shù)： 52/124頁
文件大小： 2186K
代理商： ST7FLU05MAE
Obsolete
Product(s)
- Obsolete
Product(s)
ST7LUS5, ST7LU05, ST7LU09
Supply, reset and clock management
33/124
6.3
Reset sequence manager (RSM)
6.3.1
Introduction
The reset sequence manager includes three reset sources as shown in Figure 15:
●
External RESET source pulse
●
Internal LVD reset (low voltage detection)
●
Internal watchdog reset
Note:
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to Figure 15.
These sources act on the RESET pin which is always kept low during the delay phase.
The reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
Figure 11.
Reset block diagram
1.
See Illegal opcode reset on page 99 for more details on illegal opcode reset conditions.
The basic reset sequence consists of three phases as shown in Figure 16:
●
Active phase depending on the reset source
●
64 CPU clock cycle delay
●
Reset vector fetch
Caution:
When the ST7 is unprogrammed or fully erased, the Flash is blank and the reset vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
The 64 CPU clock cycle delay allows the oscillator to stabilize and ensures that recovery
has taken place from the reset state.
The reset vector fetch phase duration is 2 clock cycles.
Figure 12.
Reset sequence phases
RESET
RON
VDD
Internal
reset
Filter
Pulse
generator
LVD reset
Watchdog reset
Illegal opcode reset(1)
Reset
Active phase
Internal reset
64 clock cycles
Fetch
vector
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