參數(shù)資料
型號(hào)： ST7FLU05MAE
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO8
封裝： 0.150 INCH, LEAD FREE, PLASTIC, SOP-8
文件頁數(shù)： 55/124頁
文件大?。?/td> 2186K
代理商： ST7FLU05MAE
Obsolete
Product(s)
- Obsolete
Product(s)
Supply, reset and clock management
ST7LUS5, ST7LU05, ST7LU09
36/124
6.4
Register description
6.4.1
Multiplexed I/O reset control register 1 (MUXCR1)
6.4.2
Multiplexed I/O reset control register 0 (MUXCR0)
MUXCR1
Reset value: 0000 0000 (00h)
765432
1
0
MIR[15:8]
Read/write once only
MUXCR0
Reset value: 0000 0000 (00h)
7
654
32
10
MIR[7:0]
Read/write once only
Table 13.
MUXCRx register description
Bit
Name
Function
15:0 MIR[15:0]
This 16-bit register is read/write by software but can be written only once between
two reset events. It is cleared by hardware after a reset. When both MUXCR0 and
MUXCR1 registers are at 00h, the multiplexed PA3/RESET pin acts as RESET. To
configure this pin as output (Port A3), write 55h to MUXCR0 and AAh to MUXCR1.
These registers are one-time writable only.
– To configure PA3 as general purpose output:
After power-on/reset, the application program has to configure the I/O port by
writing to these registers as described above. Once the pin is configured as an
I/O output, it cannot be changed back to a RESET pin by the application code.
– To configure PA3 as RESET:
An internally generated reset (such as POR, LVD, WDG, illegal opcode) will clear
the two registers and the pin will act again as a reset function. Otherwise, a
power-down is required to put the pin back in reset configuration.
Table 14.
Multiplexed I/O register map and reset values
Address (Hex.)
Register label
76543210
0047h
MUXCR0
Reset value
MIR7
0
MIR6
0
MIR5
0
MIR4
0
MIR3
0
MIR2
0
MIR1
0
MIR0
0
0048h
MUXCR1
Reset value
MIR15
0
MIR14
0
MIR13
0
MIR12
0
MIR11
0
MIR10
0
MIR9
0
MIR8
0
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