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參數(shù)資料
| 型號(hào)： | ST7FLU05MAE |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO8 |
| 封裝： | 0.150 INCH, LEAD FREE, PLASTIC, SOP-8 |
| 文件頁(yè)數(shù)： | 87/124頁(yè) |
| 文件大?。?/td> | 2186K |
| 代理商： | ST7FLU05MAE |
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Obsolete
Product(s)
- Obsolete
Product(s)
ST7LUS5, ST7LU05, ST7LU09
On-chip peripherals
65/124
Note:
Software can use the timebase feature to set the WDGD bit at 1 or 2 ms intervals.
A watchdog reset can be forced at any time by setting the WDGRF bit. To generate a forced
watchdog reset, first watchdog has to be activated by setting the WDGE bit and then the
WDGRF bit has to be set.
The WDGRF bit also acts as a flag, indicating that the watchdog was the source of the reset.
It is automatically cleared after it has been read.
Caution:
When the WDGRF bit is set, software must clear it, otherwise the next time the watchdog is
enabled (by hardware or software), the microcontroller will be immediately reset.
Hardware watchdog option
If hardware watchdog is selected by option byte, the watchdog is always active and the
WDGE bit in the LTCSR is not used.
Refer to the option byte description in Chapter 14: Device configuration and ordering
information.
Using halt mode with the watchdog (option)
If the watchdog reset on halt option is not selected by option byte, the halt mode can be
used when the watchdog is enabled.
In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the lite
timer stops counting and is no longer able to generate a watchdog reset until the
microcontroller receives an external interrupt or a reset.
If an external interrupt is received, the WDG restarts counting after 64 CPU clocks. If a reset
is generated, the watchdog is disabled (reset state).
If halt mode with watchdog is enabled by option byte (no watchdog reset on HALT
instruction), it is recommended before executing the HALT instruction to refresh the WDG
counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
Figure 30.
Watchdog timing diagram
tWDG
fWDG
Internal
watchdog
RESET
WDGD bit
Software sets
WDGD bit
Hardware clears
WDGD bit
Watchdog RESET
(2ms @ 8 MHz fOSC)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ST7FLU09MCE | 制造商:STMicroelectronics 功能描述: |
| ST7FMC1K2B3 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-bit MCU with nested interrupts, Flash, 10-bit ADC, brushless motor control, five timers, SPI, LINSCI? |
| ST7FMC1K2B6 | 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST7FMC1K2T3 | 功能描述:8位微控制器 -MCU ST7MC1/ST7MC2 8B MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST7FMC1K2T6 | 功能描述:8位微控制器 -MCU 8K Flash 384 RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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