參數(shù)資料
型號(hào)： ST7FLU05MAE
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO8
封裝： 0.150 INCH, LEAD FREE, PLASTIC, SOP-8
文件頁數(shù)： 69/124頁
文件大?。?/td> 2186K
代理商： ST7FLU05MAE
Obsolete
Product(s)
- Obsolete
Product(s)
ST7LUS5, ST7LU05, ST7LU09
Power saving modes
49/124
Figure 21.
Active halt mode flowchart
1.
Peripherals clocked with an external clock source can still be active.
2.
Only the lite timer RTC and auto-reload timer interrupts can exit the MCU from active halt mode.
3.
Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.
8.4.2
Halt mode
The halt mode is the lowest power consumption mode of the MCU. It is entered by executing
the HALT instruction when active halt mode is disabled.
The MCU can exit halt mode on reception of either a specific interrupt (see Table 15:
Interrupt mapping on page 46) or a reset. When exiting halt mode by means of a reset or an
interrupt, the main oscillator is immediately turned on and the 64 CPU cycle delay is used to
stabilize it. After the start up delay, the CPU resumes operation by servicing the interrupt or
by fetching the reset vector which woke it up (see Figure 30).
When entering halt mode, the I bit in the CC register is forced to 0 to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes immediately.
In halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).
HALT instruction
Reset
Interrupt(2)
Y
N
Y
CPU
Oscillator
Peripherals(1)
Ibit
On
Off
0
Off
Fetch reset vector
or service interrupt
CPU
Oscillator
Peripherals(1)
Ibit
On
Off
X(3)
On
CPU
Oscillator
Peripherals
Ibits
On
X(3)
On
64 CPU clock cycle
delay
(active halt enabled)
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