參數(shù)資料
型號(hào)： ST7FLU05MAE
廠商： STMICROELECTRONICS
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO8
封裝： 0.150 INCH, LEAD FREE, PLASTIC, SOP-8
文件頁(yè)數(shù)： 62/124頁(yè)
文件大?。?/td> 2186K
代理商： ST7FLU05MAE
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Obsolete
Product(s)
- Obsolete
Product(s)
Interrupts
ST7LUS5, ST7LU05, ST7LU09
42/124
Note:
1
These 8 bits can be written only when the I bit in the CC register is set.
2
Changing the sensitivity of a particular external interrupt clears this pending interrupt. This
can be used to clear unwanted pending interrupts. Refer to section External interrupt
function on page 66.
3
IS4[1:0] = 01 is the only safe configuration to avoid a spurious interrupt in Halt and AWUFH
modes.
7.4
System integrity management (SI)
The system integrity management block contains the low voltage detector (LVD) function. It
is managed by the SICSR register.
Note:
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to Illegal opcode reset on page 99 for further details.
7.4.1
Low voltage detector (LVD)
The low voltage detector function (LVD) generates a static reset when the VDD supply
voltage is below a VIT-(LVD) reference value. This means that it secures the power-up as well
as the power-down keeping the ST7 in reset.
The VIT-(LVD) reference value for a voltage drop is lower than the VIT+(LVD) reference value
for power-on in order to avoid a parasitic reset when the MCU starts running and sinks
current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when VDD is below:
●
VIT+(LVD) when VDD is rising
●
VIT-(LVD) when VDD is falling
The LVD function is illustrated in Figure 19.
The high voltage threshold can be activated by option byte. See Section 14.1 on page 131.
Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-(LVD),
the MCU can only be in two modes:
●
under full software control
●
in static safe reset
In these conditions, secure operation is always ensured for the application without the need
for external reset hardware.
During a low voltage detector reset, the RESET pin is held low, thus permitting the MCU to
reset other devices.
Table 18.
Interrupt sensitivity bits
ISx1
ISx0
External interrupt sensitivity
0
Falling edge and low level
0
1
Rising edge only
1
0
Falling edge only
1
Rising and falling edge
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