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參數(shù)資料
| 型號： | ST7FLU05MAE |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO8 |
| 封裝： | 0.150 INCH, LEAD FREE, PLASTIC, SOP-8 |
| 文件頁數(shù)： | 16/124頁 |
| 文件大小： | 2186K |
| 代理商： | ST7FLU05MAE |
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Product(s)
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Product(s)
Electrical characteristics
ST7LUS5, ST7LU05, ST7LU09
112/124
Figure 57.
RESET pin protection when LVD is enabled(1)(2)(3)(4)
1.
- The reset network protects the device against parasitic resets.
- The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad.
Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
- Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin
can go below the VIL max. level specified in Table 85 on page 123. Otherwise the reset will not be taken
into account internally.
- Because the reset circuit is designed to allow the internal reset to be output in the RESET pin, the user
must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for
IINJ(RESET) in Table 63 on page 104.
2.
When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-
down capacitor is required to filter noise on the reset line.
3.
In case a capacitive power supply is used, it is recommended to connect a 1M
pull-down resistor to the
RESET pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will
add 5A to the power consumption of the MCU).
4.
Tips when using the LVD:
A. Check that all recommendations related to ICCCLK and reset circuit have been applied (see caution in
Table 2 on page 15 and notes above)
B. Check that the power supply is properly decoupled (100nF + 10F close to the MCU). Refer to AN1709
and AN2017. If this cannot be done, it is recommended to put a 100nF + 1M
pull-down on the RESET pin.
C. The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up
marginality. In most cases, steps A and B above are sufficient for a robust solution. Otherwise: replace
10nF pull-down on the RESET pin with a 5F to 20F capacitor.
Figure 58.
RESET pin protection when LVD is disabled(1)
1.
The reset network protects the device against parasitic resets.
The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad.
Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin
can go below the VIL max. level specified in Table 85 on page 123. Otherwise the reset will not be taken
into account internally.
Because the reset circuit is designed to allow the internal reset to be output in the RESET pin, the user
must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for
IINJ(RESET) in Table 63 on page 104.
2.
Please refer to Illegal opcode reset on page 99 for more details on illegal opcode reset conditions.
ST7XXX
Pulse
generator
Filter
RON
VDD
Internal
reset
External
Required
1M
Optional
(note 3)
Watchdog
LVD reset
Illegal opcode(5)
0.1F
0.01F
external
reset
circuit
User
Required
ST7XXX
Pulse
generator
Filter
RON
VDD
Internal
reset
Watchdog
Illegal opcode(2)
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