參數(shù)資料
型號: ST7FLCD1
廠商: 意法半導體
英文描述: 8-bit MCU for LCD Monitors with 60 KBytes Flash, 2 KBytes RAM, 2 DDC Ports and Infrared Controller
中文描述: 8位微控制器的液晶顯示器為60千字節(jié)閃存,2千字節(jié)RAM,2個DDC的港口和紅外線控制器
文件頁數(shù): 92/95頁
文件大?。?/td> 633K
代理商: ST7FLCD1
Electrical Characteristics
ST7FLCD1
92/95
17.8
I2C/DDC Bus Timings
Note:1. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge
the undefined region of the falling edge of SCL.
2. The maximum hold time of the START condition has only to be met if the interface does not stretch
the low period of SCL signal.
3. Cb = total capacitance of one bus line in pF.
4. I2C parameters compliant with I2C Bus Specification for speeds up to 400 kHz only. Faster speeds
are at user responsibility.
Symbol
Parameter
Standard I2C
Fast I2C
Unit
Min.
Max.
Min.
Max.
t
BUF
Bus free time between a STOP and START
condition
4.7
1.3
ms
t
HD:STA
Hold time START condition. After this period, the
first clock pulse is generated
4.0
0.6
s
t
LOW
LOW period of the SCL clock
4.7
1.3
s
t
HIGH
HIGH period of the SCL clock
4.0
0.6
s
t
SU:STA
Set-up time for a repeated START condition
4.7
0.6
s
t
HD:DAT
Data hold time
0 (1)
0 (1)
0.9(2)
ns
t
SU:DAT
Data set-up time
250
100
ns
t
R
Rise time of both SDA and SCL signals
1000
20+0.1Cb
300
ns
t
F
Fall time of both SDA and SCL signals
300
20+0.1Cb
300
ns
t
SU
:
STO
Set-up time for STOP condition
4.0
0.6
ns
Cb
Capacitive load for each bus line
400
400
pF
Figure 44: I2C Bus Timing
tBUF
tLOW
tHIGH
tHD,STA
tR
tF
tSU,STA
tHD,DAT
tSU,DAT
tSU,STO
SDA
SCL
SDA
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