參數(shù)資料
型號(hào): ST7FLCD1
廠商: 意法半導(dǎo)體
英文描述: 8-bit MCU for LCD Monitors with 60 KBytes Flash, 2 KBytes RAM, 2 DDC Ports and Infrared Controller
中文描述: 8位微控制器的液晶顯示器為60千字節(jié)閃存,2千字節(jié)RAM,2個(gè)DDC的港口和紅外線控制器
文件頁數(shù): 83/95頁
文件大?。?/td> 633K
代理商: ST7FLCD1
83/95
ST7FLCD1
Infrared Preprocessor (IFR)
15
Infrared Preprocessor (IFR)
The Infrared Preprocessor measures the intervals between 2 adjacent edges of a serial input.
15.1
Main Features
Interval measurement between 2 edges (Time Base = 12.5 kHz) @ f
CPU
= 8 MHz
Choice of active edge
Glitch filter
Overflow detection (20.4 ms = 255/12.5 kHz)
Maskable interrupt
15.2
Functional Description
The IR Preprocessor measures the interval between two adjacent edges of the IFR input signal.
The POSED and NEGED bits determine if the intervals of interest involve:
consecutive positive edges,
negative edges,
or any pair of edges as described in
Table 30
.
The measurement is a count resulting from a 12.5 kHz clock. Therefore, any pulse width that is less
than 80 μs cannot be detected.
Whenever an edge of the specified polarity is detected, the count accumulated since the previously
detected edge is latched into the IFRDR register, an interrupt is generated and the counter is reset.
If an edge is not detected within 20.4 ms (f
CPU
= 8 MHz) and the count reaches its maximum value
of 255, it is latched immediately. The internal interrupt flag and also an internal overflow flag are set.
The latch content remains unchanged as long as the overflow flag is set.
The count stored in the latch register is overwritten in case the microcontroller fails to execute the
read before the next edge. Writing to the IFRDR register clears the interrupt and internal overflow
flag.
Figure 43: IFR Block Diagram
Filter Pulse
Edge Detection
8-bit Counter
8-bit Latch
FLSEL POSED NEGED
Interrupt
Clock Generation
12.5 kHz
IFR
fCPU
ITE
IFRCR
IFRDR
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