參數(shù)資料
型號: ST7FLCD1
廠商: 意法半導(dǎo)體
英文描述: 8-bit MCU for LCD Monitors with 60 KBytes Flash, 2 KBytes RAM, 2 DDC Ports and Infrared Controller
中文描述: 8位微控制器的液晶顯示器為60千字節(jié)閃存,2千字節(jié)RAM,2個DDC的港口和紅外線控制器
文件頁數(shù): 47/95頁
文件大小: 633K
代理商: ST7FLCD1
47/95
ST7FLCD1
PWM Generator
DUTY CYCLE REGISTERS (PWMDCRx)
Read/Write
Reset Value 0000 0000 (00h)
Bits [7:0] = DC[7:0]
Duty Cycle Data
These bits are set and cleared by software.
A DCRx register is associated with the DCRix register of each PWM channel to determine the
second edge location of the PWM signal (the first edge location is common to all 4 channels and
given by the ARR register). These DCR registers allow the duty cycle to be set independently for
each PWM channel.
CONTROL REGISTER A (PWMCRA)
Read/Write
Reset Value: 0000 0000 (00h)
Bits [7:4] = OE [3:0]
PWM Output Enable.
These bits are set and cleared by software. They enable or disable the PWM output channels
independently acting on the corresponding I/O pin.
0
the PWM pin is a general I/O.
1
the PWM pin is driven by the PWM peripheral.
Bits [3:0] = OP[3:0]
PWM Output Polarity.
These bits are set and cleared by software. They independently select the polarity of the 4 PWM
output signals.
0
positive polarity.
1
negative polarity.
Note:
When an OPx bit is modified, the PWMx output signal is immediately updated.
AUTO-RELOAD REGISTER A (PWMARRA)
Read/Write
Reset Value: 1111 1111(FFh)
Bits [7:0] = AR[7:0]
Counter Auto-Reload Data.
These bits are set and cleared by software. They are used to hold the auto-reload value which is
automatically loaded in the counter when an overflow occurs. Writing in this register reload the
PWM counter to ARR A value. At the same time, the PWM output levels are changed according to
the corresponding OPx bit in the PWMCR register.
7
6
5
4
3
2
1
0
DC7
DC6
DC5
DC4
DC3
DC2
DC1
DC0
7
6
5
4
3
2
1
0
OE3
OE2
OE1
OE0
OP3
OP2
OP1
OP0
7
6
5
4
3
2
1
0
AR73
AR6
AR5
AR4
AR3
AR2
AR1
AR0
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