- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382553 > ST7FLCD1 (意法半導(dǎo)體) 8-bit MCU for LCD Monitors with 60 KBytes Flash, 2 KBytes RAM, 2 DDC Ports and Infrared Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | ST7FLCD1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-bit MCU for LCD Monitors with 60 KBytes Flash, 2 KBytes RAM, 2 DDC Ports and Infrared Controller |
| 中文描述： | 8位微控制器的液晶顯示器為60千字節(jié)閃存，2千字節(jié)RAM，2個(gè)DDC的港口和紅外線控制器 |
| 文件頁(yè)數(shù)： | 54/95頁(yè) |
| 文件大?。?/td> | 633K |
| 代理商： | ST7FLCD1 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)當(dāng)前第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)
I2C Single-Master Bus Interface
ST7FLCD1
54/95
10.4
Functional Description (Master Mode)
By default, the I2C interface operates in Idle mode (M/IDL bit is cleared) except when it initiates a
transmit or receive sequence.
To switch from default Idle mode to Master mode a Start condition must be generated.
Setting the START bit causes the interface to switch to Master mode (M/IDL bit set) and generates
a Start condition.
Once the Start condition is sent, the EVF and SB bits are set by hardware and an interrupt is
generated if the ITE bit is set.
Then the master waits for a read of the SR register followed by a write in the DR register with the
Slave address byte, holding the SCL line low (EV1).
Then the slave address byte is sent to the SDA line via the internal shift register.
After completion of this transfer (and the reception of an acknowledge from the slave if the ACK bit
is set), the EVF bit is set by hardware and an interrupt is generated if the ITE bit is set.
Then the master waits for a read of the SR register followed by a write in the CR register (for
example set PE bit), holding the SCL line low (EV2).
Next the master must enter Receiver or Transmitter mode.
10.5
Transfer Sequencing
10.5.1 Master Receiver
Following the address transmission and after SR and CR registers have been accessed, the master
receives bytes from the SDA line into the DR register via the internal shift register. After each byte
the interface generates in sequence:
●
an Acknowledge pulse if the ACK bit is set
●
EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR register followed by a read of the DR register, holding
the SCL line low (EV3).
To close the communication, before reading the last byte from the DR register, set the STOP bit to
generate the Stop condition. The interface automatically returns to Idle mode (M/IDL bit cleared).
Note:
In order to generate the non-acknowledge pulse after the last received data byte, the ACK bit must
be cleared just before reading the second last data byte.
10.5.2 Master Transmitter
Following the address transmission and after SR register has been read, the master sends bytes
from the DR register to the SDA line via the internal shift register.
The master waits for a read of the SR register followed by a write in the DR register, holding the SCL
line low (EV4).
When the acknowledge bit is received, the interface sets the EVF and BTF bits with an interrupt if
the ITE bit is set.
To close the communication, after writing the last byte to the DR register, set the STOP bit to
generate the Stop condition. The interface automatically returns to Idle mode (M/IDL bit cleared).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST7FLIT19B | 8-Bit MCU With Single Voltage Flash Memory, Data EEPROM, ADC, 5 Timers, SPI(內(nèi)部RC,PLL,ADC,ROP,ICP, IAP,SPI的8位MCU) |
| ST7FLITE10F1B6 | 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 4 TIMERS, SPI |
| ST7FLITE19F1M6 | CLUSTER PANEL,RJ-11 W/ (12) 4- |
| ST7LITE1 | 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 4 TIMERS, SPI |
| ST7FLITE15F1B6 | 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 4 TIMERS, SPI |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST7FLCD1_05 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-bit MCU for LCD Monitors with 60 KBytes Flash,2 KBytes RAM, 2 DDC Ports and Infrared Controller |
| ST7FLI15BF1U6 | 功能描述:8位微控制器 -MCU 8-Bit MCU w/ Single Volt Flash RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST7FLI15BF1U6TR | 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST7FLI19BF1M3TR | 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST7FLI19BF1U6TR | 功能描述:8位微控制器 -MCU 8-Bit MCU w/ Single Volt Flash RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。