
ST7FLCD1
4/95
10.5.1
10.5.2
Master Receiver .................................................................................................................................54
Master Transmitter .............................................................................................................................54
10.6
Register Description ...........................................................................................................56
Chapter 11
Display Data Channel Interfaces (DDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
11.1
Introduction ........................................................................................................................60
11.2
DDC Interface Features .....................................................................................................60
11.2.1
Hardware DDC2B Interface Features ................................................................................................60
11.2.2
DDC/CI Factory Interface Features ...................................................................................................60
11.3
Signal Description ..............................................................................................................62
11.3.1
Serial Data (SDA) ..............................................................................................................................62
11.3.2
Serial Clock (SCL) .............................................................................................................................62
11.4
DDC Standard ....................................................................................................................62
11.4.1
DDC2B Interface ................................................................................................................................62
11.4.2
Mode Description ...............................................................................................................................63
11.5
DDC/CI Factory Alignment Interface ..................................................................................66
11.5.1
I2C Modes ..........................................................................................................................................66
11.6
Transfer Sequencing ..........................................................................................................68
11.7
Register Description ...........................................................................................................69
Chapter 12
Watchdog Timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
12.1
Introduction ........................................................................................................................75
12.2
Main Features ....................................................................................................................75
12.3
Main Watchdog Counter ....................................................................................................75
12.4
Lock-up Counter .................................................................................................................76
12.5
Interrupts ............................................................................................................................76
12.6
Register Description ...........................................................................................................76
Chapter 13
8-bit Timer (TIMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
13.1
Introduction ........................................................................................................................77
13.2
Main Features ....................................................................................................................77
13.3
Functional Description ........................................................................................................77
13.4
Register Description ...........................................................................................................78
Chapter 14
8-bit Timer with External Trigger (TIMB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
14.1
Introduction ........................................................................................................................80
14.2
Main Features ....................................................................................................................80
14.3
Functional Description ........................................................................................................80