參數(shù)資料
型號: ST7FLCD1
廠商: 意法半導體
英文描述: 8-bit MCU for LCD Monitors with 60 KBytes Flash, 2 KBytes RAM, 2 DDC Ports and Infrared Controller
中文描述: 8位微控制器的液晶顯示器為60千字節(jié)閃存,2千字節(jié)RAM,2個DDC的港口和紅外線控制器
文件頁數(shù): 81/95頁
文件大?。?/td> 633K
代理商: ST7FLCD1
81/95
ST7FLCD1
8-bit Timer with External Trigger (TIMB)
The four possible operating modes are described in
Table 28
.
Note:1. The downcounter value cannot be read.
2. Change the EXT value to exit the External One-shot mode.
TIMER B CONTROL STATUS REGISTER (TIMCSRB)
Read/Write
Reset value: (00h)
Bits [7:6] = TB[1:0]
Time Base period selection
These bits are set and cleared by software.
00 Time base period = t
TIMER
(16 μs @ 8 MHz)
01 Time base period = t
TIMER
x 8 (128 μs @ 8 MHz)
10 Time base period = t
TIMER
x 16 (256 μs @ 8 MHz)
11 Reserved
Bit 5 = OVF
Timer Overflow Flag
This bit is set by hardware. An interrupt is generated if OVFE = 1. It must be cleared by reading the
TIMCSRB register.
0
No timer overflow
1
The free running downcounter rolled over from 00h
Table 28: Timer Operating Mode
TAR
EXT
Timer mode
0
0
One-shot
after the TIMCPRB register write (no auto reload)
0
1
One-shot
after the external signal detection (no auto reload).
Only the very first external pulse triggers the countdown (
Note 2
)
1
0
Downcounter
auto-reload
when 00h reached
Downcounter reloaded with TIMCPRB register value, count-down restarts
1
1
One-shot
for each external signal detection.
Downcounter preloaded with TIMCPRB when 00h reached.
Countdown restarts after the next external signal detection.
Table 29: Timer Controller Register Map
Address
Reset
R/W
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0038h
00h
R/W
TIMCSRB
TB1
TB0
OVF
OVFE
TAR
EXT
EDG
EEF
0039h
01h
R/W
TIMCPRB
PR7
PR6
PR5
PR4
PR3
PR2
PR1
PR0
7
0
TB1
TB0
OVF
OVFE
TAR
EXT
EDG
EEF
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